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TPMC310 User Manual Issue 1.1.5
Page 12 of 22
4 PCI9030 Target Chip
4.1 PCI Configuration Registers (PCR)
4.1.1 PCI9030 PCI Header
Write ‘0’ to all unused (Reserved) bits
PCI CFG
Register
Address
31 24
23 16
15 8
7 0
PCI
writeable
Initial Values
(Hex Values)
0x00
Device ID
Vendor ID
N
0136 1498
0x04
Status
Command
Y
0280 0000
0x08
Class Code
Revision ID
N
028000 00
0x0C BIST Header
Type
PCI Latency
Timer
Cache Line
Size
Y[7:0]
00 00 00 00
0x10
PCI Base Address 0 for MEM Mapped Config. Registers
Y
FFFFFF80
0x14
PCI Base Address 1 for I/O Mapped Config. Registers
Y
FFFFFF81
0x18
PCI Base Address 2 for Local Address Space 0
Y
FFFFFFF0
0x1C
PCI Base Address 3 for Local Address Space 1
Y
FFFFFE00
0x20
PCI Base Address 4 for Local Address Space 2
Y
00000000
0x24
PCI Base Address 5 for Local Address Space 3
Y
00000000
0x28
PCI CardBus Information Structure Pointer
N
00000000
0x2C
Subsystem ID
Subsystem Vendor ID
N
s.b. 1498
0x30
PCI Base Address for Local Expansion ROM
Y
00000000
0x34
Reserved
New Cap. Ptr.
N
000000 40
0x38 Reserved N
00000000
0x3C Max_Lat Min_Gnt Interrupt
Pin
Interrupt Line
Y[7:0]
00 00 01 00
0x40
PM Cap.
PM Nxt Cap.
PM Cap. ID
N
4801 00 01
0x44
PM Data
PM CSR EXT
PM CSR
Y
00 00 0000
0x48
Reserved
HS CSR
HS Nxt Cap.
HS Cap. ID
Y[23:16]
00 00 00 06
0x4C
VPD Address
VPD Nxt Cap.
VPD Cap. ID
Y[31:16]
0000 00 03
0x50 VPD
Data Y
00000000
Table 4-1 : PCI9030 PCI Header
Subsystem-ID: TPMC310-10:
0x000A