Tews Technologies TIP606, Руководство пользователя

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TIP606 User Manual Issue 1.3 Page 10 of 15
4.3 Global Control Register (GLBCONT)
After power up or reset all bits of this register are reset to ‘0’.
Bit Symbol Description Access Reset
Value
7 Global interrupt flag
1 = an interrupt request of at least one of the 16 input
channels is pending.
Bit will be cleared if the appropriate interrupt is acknowledged
by writing ‘1’ to one of the interrupt status registers. R
6:3 Not used, undefined during reads R/W
2 Debounce control bit
1 = enables debounce circuit for all 16 inputs
0 = disables debounce circuit
R/W
1 Not used, undefined during reads R/W
0 Global interrupt enable bit
1 = enables all possible interrupts of the TIP606 on interrupt
request line INTREQ0# of the IP bus
0 = disables all interrupts R/W
Figure 4-3 : Global Control Register (GLBCONT)
4.4 Interrupt Enable Register Rising Edge
(INTENALH)
Bit Symbol Description Access Reset
Value
15
.
.
.
0 Interrupt enable bit of corresponding channel for the rising
edge
Bit 0 enables interrupts of input channel 1 and bit 15 enables
interrupt of input channel 15 rising edge.
1 = interrupt enabled
0 = interrupt disabled R/W
Figure 4-4 : Interrupt Enable Register Rising Edge (INTENALH)
An interrupt on interrupt request line INTREQ0# of the IP bus is only generated if the global
interrupt enable bit of the Global Control Register is set to ‘1’. After power up or reset all bits of
this register are reset to ‘0’.