Teridian 73S1217F, Руководство пользователя, Страница: 19 / 34

UG_1217F_040 73S1217F Evaluation Board User’s Guide
Rev. 2.4 19
4.3 Schematic
1 2 3 4 5 6 7 8 9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
J12
PROTO TY PE AREA
1 2 3
JP16
1
TP1
1
TP4
R8
10
Y 1
12.000MHz
1 2
S27
SW
VDD
OSC_OUT_12 OSC_OUT_12 OSC_IN_12 OSC_IN_12
OSC_OUT_12
OSC_IN_12
OSC_OUT_32
OSC_IN_32
1
G5
1
2
3
JP9
GND
COL4
1
2
3
JP21
+ C28
4.7uF
COL1
COL3
COL2
COL0
RST_EMUL
C30
0.1uF
1 2 3
JP2
1
2
3
4
5
6
TP27
HEADER 6
5V
R34
1M
+
C29
1uF
GND
GND
4
1
G6
ANALOG IN
RXD
8010R INT
SIO
IO
POWER
1
2
TP31
RXD
VCC
TXD
SCLK
C39
22pF
USR7
USR2
VBAT (4.0 - 6.5VDC) J3
Banana
L1
10uH
GND
VBAT
EXT
+5VDC
VPC
ROW4 ROW4
8
RESET
VP
DNI
3
1
2
3
JP15
HEADER 3_0
F3
TERIDIAN LOGO
GND
C18
1uF
USR7
STATUS INDICATOR
+ C27
10uF
VBAT
SELECT
SCx_CLK and Vcc tracks
should be routed away
from other Smart card
signalsand should be
surrounded by GND.
SMARTCARD
SLOT #2
USR5
RXD
C14, C15, C16, C18,
C20 and C21 should be
located close to the
Smart Card Connector
INT2
2
MOUNT HOLES FOR STAND OFFS
1 2
3 4
TP22
HEADER 2X2
DNI
1
2
3
4
5
6
7
8
9
10
J7
TSM_110_01_L_SV
C37
VDD
1
1
2
2
3
3
PJ1
+5VDC
VDD
INT3
TXD
VBAT
VD
D
6
8
RESET
1
SEC
2
ISBR
3
SCL
5
SDA
6
NC/X32OUT
7
NC/X32IN
8
GND
9
X12IN
10
X12OUT
11
COL0
12
COL1
13
COL2
14
ANAIN
15
COL3
16
RXD
17
T
XD
1
8
C
O
L4
1
9
US
R7
2
0
RO
W0
2
1
RO
W1
2
2
US
R6
2
3
RO
W2
2
4
GN
D
2
5
NC/
DP
2
6
NC/
DM
2
7
VD
D
2
8
US
R5
2
9
US
R4
3
0
US
R3
3
1
US
R2
3
2
RO
W3
3
3
US
R1
3
4
USR0
35
ROW4
36
ROW5
37
ERST
38
TCLK
39
VDD
40
TBUS3
41
GND
42
RXTX
43
TBUS2
44
SCLK
45
TBUS1
46
SIO
47
INT3
48
INT2
49
TBUS0
50
TEST
51
O
FF_
RE
Q
5
2
PR
ES
5
3
VP
5
4
C
L
K
5
5
GN
D
5
6
R
ST
5
7
VC
C
5
8
C8
/A
UX
2
5
9
C4
/A
UX
1
6
0
I/
O
6
1
VBU
S
6
2
ON
_OF
F
6
3
VBAT
6
4
VPC
6
5
L
IN
6
6
GN
D
6
7
S
LU
G
6
9
LED0
4
U6
1217/10
1
2
3
JP13
1
2
3
JP11
SCL
SDA
R16 R17 R15
D8
LED
VDD
R35
680
TBUS[1]
VPC
+5VDC
UnReg
.
USR1
GND
CLK
1
6
2
7
3
8
4
9
5
P1
DB9_RS232
C43
1000pF
+5V SOURCE
SELECT
SCx_CLK and Vcc tracks
should be routed away
from other Smart card
signalsand should be
surrounded by GND.
C33
0.1uF
INT2
B
SIO
TBUS[0]
UP
ROW5 ROW5 ROW5 ROW5 ROW5 ROW5
RXTX
1 2 3
JP1
These test pins should be located between two rows (4
pads each) of SC connector and signal pins locate within
5mm from pads.
CLK track should be routed away from RST and C4.
F2
F
CLK
1
TP2
Y 2
32.768kHz
SC8
C32
0.1uF
C35
0.1uF
+5V
C2 should be as
close as possible
to pin 66
5V
ISY NC/BRKRQ
C34
0.1uF
(RED)
ON_OFF
X
CLR
INT3
W
C1
1
C2
2
C3
3
C5
4
C6
5
C7
6
SW1
7
SW2
8
J1
SIM/SAM Connector
USR7/SDA
USR0
LCD
BRIGHTNESS
ADJUST
VDD
VPC (2.7-6.5VDC)
C8
USR3
CARD DET
VPC
EXTERNAL POWER
SUPPLY
USR5
GND
VBUS
OPTIONAL LCD DISPLAY SYSTEM
16 CHARACTER BY 2 LINES
Z
30-SWITCH
KEYPAD
C3, C4 and C5
should be as
close as possible
to VDD pins on U6
C31
0.1uF
5 VDC
UnReg
VCC
ROW1 ROW1 ROW1 ROW1 ROW1 ROW1
F1
C16
0.47uF
(BLK)
1 2
JP3
HEADER 2
INT2
TXD
USR1
VDD
1
G7
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
TP25
HEADER 2 x 4
VDD
/
SCLK
+5VDC
UnReg
DNI
ROW0
1
2
TP6
5V
D-
2
D+
3
GND
4
VCC
1
GND
5
GND
6
J6
USB_CONN_4
C22
22pF
VDD
C3
0.1uF
C4
0.1uF
ROW5
C5
0.1uF
VDD
ROW4
1 2
JP4
HEADER 2
+
C2
10uF
+
C7
10uF
C38
22pF
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
TP10
HEADER 2 x 4
C1
1
C2
2
C3
3
C5
4
C6
5
C7
6
SW1
7
SW2
8
J10
SIM/SAM Connector
1
TP18
SEC
1
G8
VO
3
VD
D
2
D
B0
7
NC
1
5
GN
D
1
RS
4
R/
W*
5
E
6
D
B7
1
4
D
B6
1
3
D
B5
1
2
D
B4
1
1
D
B3
1
0
D
B2
9
D
B1
8
U5
MDL-16265
TXD
RXD
RO
W3
RO
W2
VBU
S
RO
W1
RO
W0
C
O
L4
R2 24
COL3
VDD
USR2
USR7
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
J11
Emulator IF
USR3
USR1
USR0
USR5
USR6
USR4
SAD0
1
SAD1
2
SAD2
3
GND
4
N/C
5
VPC
6
N/C
7
AUX2
12
N/C
8
N/C
9
PRES
10
I/O
11
AUX1
13
GND
14
CLK
15
RST
16
VCC
17
VDD_ADJ
18
SCL
19
SDA
20
VDD
21
GND
22
INT
23
AUX2UC
28
AUX1UC
27
XTALOUT
25
XTALIN
24
I/OUC
26
73S8010R
U4
COL2
COL1
COL0
1
2
TP30
INT2
INT3
TCLK
1 2
JP10
HEADER 2
1 2
JP14
HEADER 2
1
TP35
1
G9
VDD
ROW2 ROW2 ROW2 ROW2 ROW2 ROW2
C1+
28
C1-
25
C2+
1
C2-
3
T1IN
24
T2IN
23
T3IN
22
T4IN
19
T5IN
17
R1OUTBF
16
R1OUT
21
R2OUT
20
R3OUT
18
GN
D
2
M
BAU
D
1
5
SHDNB
14
ENB
13
R3IN
11
R2IN
9
R1IN
8
T1OUT
5
T2OUT
6
T3OUT
7
T4OUT
10
T5OUT
12
V-
4
V+
27
VC
C
2
6
U7
MAX3237CAI
R4 100k
R13
3k
R12
3k
SCL SCL
R11 62
1
G1
VDD
R19 62
R18 62
R14 62
Unpopulated
& unlabled
R20 62
R21 62
R23 62
1 3
S2
SW_MOM
R22 62
US
R4
US
R1
US
R2
US
R0
US
R5
US
R3
US
R6
VDD
VDD
ROW3 ROW3 ROW3 ROW3 ROW3 ROW3
C20
27p
VCC
1
RST
2
CLK
3
C4
4
GND
5
VPP
6
I/O
7
C8
8
SW-1
9
SW-2
10
J9
Smart Card Connector
C41
22pF
C15
27p
C21
27p
SDA
SCL
GND GND
C17
0.1uF
VBAT VBAT VBAT
R5
200k
VDD
OSC_OUT_32 OSC_OUT_32 OSC_OUT_32 OSC_OUT_32
1 2 3
JP6
USR6 USR6 USR6 USR6
R25
10k
(RED)
USR6/SCL
GND
GND
USR0
+3.3V
SC4
VBUS VBUS
INT3
ROW5
ANALOG SELECT
GND
USR2
ON_OFF
C
1
D+
SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL SCL
1 3
S3
SW_MOM
GND
1
TP11
1 3
S4
SW_MOM
EXT
VPC
Length and width of USB D+ and D- tracks
should be matched and routed away from
smart card CLK and VCCs
Place R11, R14, R18,
R19, R20, R21, R22
and R23 close to U6
IO
1 3
S5
SW_MOM
ROW3
C40
22pF
1 3
S6
SW_MOM
USR4
6
Layout TP10 & TP25 as 8x2 header and TP23 and TP26 as 4x2
header. Populate 2pin header to every other rows such as
pin1-2, pin5-6, pin9-10 and pin13-14 for TP10 and TP25.
PWR_ON
+ C1
10uF
SERIAL
PORT
C4
ROW1
5
1 3
S33 SW_MOM
DOWN
8010 VPC
SELECT
1 2 3
JP7
GND
OSC_IN_32 OSC_IN_32 OSC_IN_32 OSC_IN_32
C42
22pF
GND
GND
GND
E
SDA SDA SDA SDA SDA SDA
R3 24
7
OFF_REQ
C14
27p
ENTER
ROW2
Y
D+
9
VBAT VBAT
VBUS_MON VBUS_MON VBUS_MON VBUS_MON VBUS_MON VBUS_MON
1
TP12
USR7
AUX1
D4
LED
AUX2
AUX1
LED0
AUX2
VDD
R10
10k
J2
Banana
1
2
3
JP5
1 3
S7
SW_MOM
1 2
JP12
HEADER 2
1
TP13
1 3
S12
SW_MOM
5V
1 3
S17
SW_MOM
1 3
S22
SW_MOM
1 3
S28
SW_MOM
1 3
S8
SW_MOM
1 3
S13
SW_MOM
1 3
S18
SW_MOM
1 3
S23
SW_MOM
1 3
S29
SW_MOM
1
TP14
1 3
S9
SW_MOM
1 3
S14
SW_MOM
1 3
S19
SW_MOM
R26
10k
1
SY M1
Logo
1 3
S24
SW_MOM
1 3
S30
SW_MOM
1 3
S10
SW_MOM
1 3
S15
SW_MOM
1 3
S20
SW_MOM
1
TP15
1 2
JP23
HEADER 2
1 3
S25
SW_MOM
1 3
S31
SW_MOM
1 3
S16
SW_MOM
1 3
S11
SW_MOM
1 3
S21
SW_MOM
1 3
S26
SW_MOM
1 3
S32
SW_MOM
1
TP16
VPC
USR1
USR0
USR2
1 2
D1
MBR0520L
1
TP17
USR3
USR4
USR5
5V
AUX2
GND
INT2
AUX1
5V
SIO
SCLK
1
2
3
4
5
6
7
8
9
10
J8
TSM_110_01_L_SV
C23
22pF
VCC
1
RST
2
CLK
3
C4
4
GND
5
VPP
6
I/O
7
C8
8
SW-1
9
SW-2
10
J4
Smart Card Connector
C24
22pF
C25
22pF
1
G2
GND
SHUTDOWN
SMARTCARD
SLOT #1
SC I/F EXPANSION
C4
US
R1
TXD
INT2
US
R2
GND
+5VDC
VBUS
1 2 3
JP20
J5
Banana
US
R7
US
R6
TBUS[2]
US
R5
TBUS[3] TBUS[3]
US
R4
US
R3
1
2
3
4
5
6
7
8
TP21
HEADER 8
DNI
R24
10k
DNI
1
TP3
0
VP
D
ON/CE
D-
USR4
COL2 COL3 COL1 COL1 COL0
R6
0
1
TP32
R1
0
1
G3
R7 680
R9 680
RXD
1
TP24
DP
L
US
DMI
NUS
VDD
COL4
GND
D2
LED
VDD
D3
LED
DNI
VBUS_MON VBUS_MON VBUS_MON VBUS_MON VBUS_MON VBUS_MON
VBAT
RST
D-
R27
0
1 2 3
JP8
RST
GND
C28 should
be as close
as possible
to pin 55
VCC tracks should be
wider than 0.5mm.
+5V
DPLUS
DMINUS
USR6
+5V
USR5
GND
C8
A
USR3
SEC
USR0
D5
5.1V
1
G4
+5VDC
1
2
3
4
5
TP29
HEADER 5
ROW5
ROW3
ROW0
ROW2
ROW4
ROW1
C26
0.1uF
8010 VPC
SELECT
5V
1
3
2
CW
RV1
10K
VP
+5V
Figure 7: 73S1217F Evaluation Board Electrical Schematic