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71M6513/71M6513H Demo Board User’s Manual
Page: 72 of 112
©
2005-2006 TERIDIAN Semiconductor Corporation
Revision 5.6
3.3 D6513T3D2 BOARD DESCRIPTION: JUMPERS, SWITCHES AND
TEST POINTS
The items described in the following tables refer to the flags in Table 3-6.
Item #
Reference
Designator
Name
Use
1 U7
LCD
Display
2
U5
--
The 71M6513/71M6513H chip
3
--
--
Serial number field on silk screen
4
J17
Test Point for the
Optical Interface
Five-pin header allowing access to the OPT_RX and OPT_TX
signals. Pins 1 and 2 can be used to connect a LED. Pins 3, 4,
and 5 can be used to connect a photo-transistor.
5 JP14
DIO
00
6 JP13
DIO
01
7 JP15
DIO
02
8
TP13
GND
Ground test point
9
J14
EMULATOR I/F
Connector for emulator (ADM51) or programmer (TFP-1)
10
JP10
5V, VLCD, 3.3V
Voltage selector for LCD
11 TP11
CKTEST,
GND
TMUXOUT
Test header for accessing CKTEST and TMUXOUT pins
12
TP10
GND, V1, V3P3
Plugging a jumper between pins 2 and 3 disables the watch
dog timer of the 71M6513 so that the emulator and/or flash
programmer can be used.
13
J18
V3P3, V1IN, V2IN,
GND
Plugging a jumper between pins 3 and 4 provides power to the
resistor divider R83/R86 for V1.
14
TP7
GND, VREFOUT
This header provides access to the VREF pin.
15
TP8
V3, VBIAS
This header provides access to the signal of the current
transformer used to measure the neutral current.
16
TP1
IA, V3P3
This header provides access to the signal of the current
transformer used to measure the current in phase A.
17
TP3
IB, V3P3
This header provides access to the signal of the current
transformer used to measure the current in phase B.
18
TP5
IC, V3P3
This header provides access to the signal of the current
transformer used to measure the current in phase C.
19
J10
V3_IN
Three-pin header for connecting the CT of the neutral phase.
20
J3
IA_IN
Three-pin header for connecting the CT of the phase A. Pin 3
is GND and can be used to connect a cable shield.
21
J5
IB_IN
Three-pin header for connecting the CT of the phase B.
http://www.datasheetcatalog.com/