Terasic SDI-FMC, Руководство пользователя

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SDI-FMC User Manual
49
www.terasic.com
April 22, 2019
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The LMH1983 is designed to generate a 27MHz clock for the Si5344. Terasic provides a LMH1983
configuration IP for developers to configure LMH1983 to generate the required reference clock.
The IP can be used to configure LMH1983 to generate the following clock setting in our
application:
⚫
OUT0: 27.0 MHz clock which is connected to Si5344
⚫
OUT1: 148.5 or 74.25 MHz clock which is connect co MUX DS250
⚫
OUT2: 148.35 or 74.176 MHz clock which is connected to MUX DS250
⚫
OUT3: 24.579 or 98.304 MHz clock which is connect to MUX DS250
The OUT0 clock can be used as a reference clock for the Si5344 clock generator. The LMH1983
Configuration IP provides 4 configuration modes for users to configure the LMH1983.
Figure 4-15 ,
Figure 4-16 , Figure 4-17 and Figure 4-18 show the four configuration modes provided by the
LMH1983 Configuration IP.
In MODE0, the FPGA would loopback the three H/V/F sync signals from LMH1981 to LMH1983.
Users need to provide a video signal to the VIDEO-IN BNC connector J7 on the SDI-FMC board.
For supported video formats, please refer to the datasheet of LMH1981.
Figure 4-15 MODE0: Video Genlock Timing Generation for A/V Frame Synchronizer