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Figure 4-4 Triple-Speed Ethernet Core Configuration 

In  the  Mac  Options  section,  the  MDIO  module  is  included  that  controls  the  PHY  Management 
Module associated with the MAC  block shown  in 

Figure  4-5

. The host Clock divisor is to divide 

the MAC control register interface clock to produce the MDC clock output on the MDIO interface. 
The  MAC  control  register  interface  clock  frequency  is  100  MHz  and  the  desired  MDC  clock 
frequency is 2.5 MHz, a host clock divisor of 40 should be used. 

Содержание HSMC-NET

Страница 1: ...HSMC NET Terasic HSMC NET Daughter Board User Manual ...

Страница 2: ...ram 7 Chapter 3 Board Components 9 3 1 The HSMC NET Connector 9 3 2 I2C Serial EEPROM 15 Chapter 4 Demonstrations 16 4 1 Introduction 16 4 2 How the Demonstration is built 17 4 3 System Requirements 25 4 4 Setup the Demonstration 25 4 5 Demo Operation 26 4 6 Overview 28 4 7 Nios Program 29 Chapter 5 Appendix 31 5 1 Revision History 31 5 2 Always Visit HSMC NET Webpage for New Main board 31 ...

Страница 3: ...C interfaces 1 1 1 1 F Fe ea at tu ur re es s Figure 1 1shows the photo of the HSMC NET board The important features are listed below One HSMC connector for interface conversion which is fully compatible with Cyclone III Starter Kit and DE3 host boards Duel Port Integrated 10 100 1000 Gigabit Ethernet transceiver Supports GMII MII RGMII TBI MAC interfaces for direct connection to a MAC Switch port...

Страница 4: ...b bo ou ut t t th he e K KI IT T This section describes the package content HSMC NET board x 1 System CD ROM x 1 The CD contains technical documents of the HSMC NET and one reference design along with the source code Figure 1 2 HSMC NET Package ...

Страница 5: ...g DE3 as an example shown in Figure 1 4 The HSMC NET daughter board connects to the main boards through the HSMC interface For the DE3 the HSMC NET can be connected to any DE3 s four HSTC connectors using a THCB HFF adapter card Figure 1 3 which can be found in the DE3 package Figure 1 3 THCB HFF adapter card Figure 1 4 The DE3 board connected to the HSMC NET daughter board ...

Страница 6: ...main the main board when the power is on or else the hardware could be damaged 1 1 4 4 G Ge et tt ti in ng g H He el lp p Here are some places to get help if you encounter any problem Email to support terasic com Taiwan China 886 3 550 8800 Korea 82 2 512 7661 Japan 81 428 77 7000 ...

Страница 7: ...nd block diagram 2 2 1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s The picture of the HSMC NET board is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the location of the connectors and key components Figure 2 1 The HSMC NET PCB and component diagram ...

Страница 8: ... the HSMC NET board Ethernet Transceiver J2 J3 25MHz Oscillator Y1 Y2 HSMC expansion connector J1 Marvell 88E1111 Ethernet Device U2 U3 Voltage Regulator REG1 REG2 I2C EEPORM U1 LED Configuration 2 2 2 2 B Bl lo oc ck k D Di ia ag gr ra am m Figure 2 3 shows the block diagram of the HSMC NET board ...

Страница 9: ...8 Figure 2 3 The block diagram of the HSMC NET board ...

Страница 10: ...T Th he e H HS SM MC C N NE ET T C Co on nn ne ec ct to or r This section describes pin definition of the HSMC NET interface onboard All the control and data signals of the Ethernet transmitter and receiver are connected to the HSMC connector so users can fully control the HSMC daughter board through the HSMC interface Power is derived from 3 3V and 12V of the HSMC connector ...

Страница 11: ...10 ...

Страница 12: ...11 ...

Страница 13: ...12 Figure 3 1 The pin outs on the HSMC connector The Table 3 1 below lists the HSMC signal direction and description Note The power pins are not shown in the Table 3 1 ...

Страница 14: ...input Receive data valid pin Ethernet 1 NET1_LED_LINK1000 67 input Parallel LED output for link indicator Ethernet 1 NET1_RX_CLK 68 input Receive Clock provides a clock reference Ethernet 1 NET1_TX_D1 71 output Transmit code group bit 1 Ethernet 1 NET1_TX_CLK 72 input Provides a clock reference Ethernet 1 NET1_TX_D5 73 output Transmit code group bit 5 Ethernet 1 NET1_RX_ER 74 input Receive Error p...

Страница 15: ... input Receive code group bit 5 Ethernet 0 NET0_TX_EN 121 output Transmit Enable Ethernet 0 NET0_RX_D3 122 input Receive code group bit 3 Ethernet 0 NET0_TX_D0 125 output Transmit code group bit 0 Ethernet 0 NET0_RX_D1 126 input Receive code group bit 1 Ethernet 0 NET0_TX_D4 127 output Transmit code group bit 4 Ethernet 0 NET0_RX_CLK 128 input Receive Clock provides a clock reference Ethernet 0 NE...

Страница 16: ...s configured by the I2C interface The size of the EEPROM is 2K bit which can store MAC information or user s data The Default I2C slave address is 0xA0 The detailed pin description between the HSMC connector and EEPROM is shown below in Figure 3 2 Figure 3 2 The block diagram of the EEPROM and HSMC connector Table 3 2 The pin assignments of the EEPROM U1 Table 3 2 The pin assignments of the EEPROM...

Страница 17: ...on we use DE3 as the host board connected to the HSMC NET daughter board However the HSMC NET and Cyclone III FPGA Starter Kit Demo is also available in the HSMC NET CD ROM We will illustrate how to create a simple socket server generated in Nios II using the Ethernet daughter board with the DE3 host board As indicated in the block diagram in Figure 4 1 the Nios II processor is used to communicate...

Страница 18: ... TCP IP stack uses the MicroC OS II RTOS multithreaded environment to provide immediate access to a stack for Ethernet connectivity for the Nios II processor The Nios II processor system contains an Ethernet interface or media access control MAC 4 4 2 2 H Ho ow w t th he e D De em mo on ns st tr ra at ti io on n i is s b bu ui il lt t The section describes the steps using Quartus II Nios II and SO...

Страница 19: ... HSMC NET daughter board is 2 5V Once the connection is established between DE3 board and HSMC NET board the DE3 System builder will change the I O standard of the connector to fit with the daughter board automatically The I O standard of the HSTCC male connector has been changed from 3 3 V LVTTL to 2 5V Also the DDR2_SODIMM component is added in the board list by building a connection with the DE...

Страница 20: ...cessor On Chip memory DDR2 controller JTAG UART system ID timer Triple Speed Ethernet Scatter Gather DMA controller and peripherals which are linked together contained in the Nios II hardware system that are used when building a project In the Triple Speed Ethernet IP Core configuration the interface is set to GMII interface as well as using the internal FIFO shown in Figure 4 4 ...

Страница 21: ...nt Module associated with the MAC block shown in Figure 4 5 The host Clock divisor is to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency is 100 MHz and the desired MDC clock frequency is 2 5 MHz a host clock divisor of 40 should be used ...

Страница 22: ...21 Figure 4 5 Triple Speed Ethernet MAC Options Once the Triple Speed Ethernet IP configuration has been set and necessary hardware connections has been made shown in Figure 4 6 click on generate ...

Страница 23: ...22 Figure 4 6 SOPC builder The Block diagram shows the connection for programmable 10 100 1000 Ethernet operation via GMII Figure 4 7 shows how gigabit Ethernet PHYs are connected to the MAC via GMII ...

Страница 24: ... in Quartus II is used in the Select Target Hardware section Figure 4 8 Nios II Project Simple Socket Server After the project is created open network_utilities c to modifty the flash section which uses flash to store the MAC address Since the demonstration uses DE3 host board which doesn t have flash memory the flash portion of the code can be commented out shown in Figure 4 9 as well as insertin...

Страница 25: ...e Simple Socket Server it uses GMII mode interface which we have to modify in the ins_tse_mac c code shown in Figure 4 10 Around line 327 the code marvell_cfg_gmii tse iface mi base is included in order for the Simple Socket Server to operate in GMII mode ...

Страница 26: ...ration HSMC NET DDR2 SO DIMM Bundled in the DE3 DE3 Board THCB HFF adapter card Not required for Cyclone III FPGA Starter Kit HSMC NET Demo Standard Cat 5 UTP unshielded twisted pair cable Gateway Router USB Blaster cable 4 4 4 4 S Se et tu up p t th he e D De em mo on ns st tr ra at ti io on n Figure 4 11 shows how to setup hardware for the HSMC NET Server demonstration ...

Страница 27: ...lish connection with DE3 and HSMC NET daughter board 4 4 5 5 D De em mo o O Op pe er ra at ti io on n This section describes the procedures of running the demonstration FPGA Configuration Demonstration Setup File Locations and Instructions Project directory Demo_Batch Reminder Select the appropriate DE3 Device Folder ...

Страница 28: ... cable connected to the USB Blaster port as well as connecting the Ethernet Cable from the Gateway device to the Ethernet Transceiver Open the Simple Socket Server by executing the de3_net bat file where the IP address and port number are assigned as shown below in Figure 4 12 Figure 4 12 Simple Socket Server To establish connection start the telnet client session by executing open_telnet bat file...

Страница 29: ...e HSMC NET daughter board showing what speed is connected as well as the LEDs D4 D7 blinking sequence is a lot faster connected to 1000Mbps compared to 100Mbps 4 4 6 6 O Ov ve er rv vi ie ew w This section describes the design concepts for the HSMC NET demonstration The Simple Socket Server uses the industry standard sockets interface to TCP IP It uses DHCP protocol to requests a valid IP from the...

Страница 30: ...tic supporting physical media for 1000BASE T 100BASE TX and 10BASE T Once the link is established an IP address is assigned to the Ethernet device along with the port number Through the TCP and port number the demonstration uses Telnet client to establish connection with the Simple Socket Server where it is continuously listening on the port Once the connection is established between the Telnet cl...

Страница 31: ...are device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to function The HAL API block provides the interface for the software device drivers while the MicroC OS II provides communication services to the NicheStack and the Simple Socket Server The NicheStack TCP IP Stack software block provides networking services to the application block where ...

Страница 32: ...iption 5 5 2 2 A Al lw wa ay ys s V Vi is si it t H HS SM MC C N NE ET T W We eb bp pa ag ge e f fo or r N Ne ew w M Ma ai in n b bo oa ar rd d We will be continuing providing interesting examples and labs on our HSMC NET Webpage Please visit www altera com or hsmcnet terasic com for more information Copyright 2010 Terasic Technologies All rights reserved ...

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