Terasic HAN Pilot Platform, Руководство по демонстрации

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HAN Pilot Platform
Demonstration Manual 15 www.terasic.com
September 6, 2019
Figure 2-14 shows the function block diagram of this demonstration. There are two DDR4 SDRAM
controllers. The controller uses 266.667 MHz as a reference clock. It generates one 1066MHz clock
as memory clock from the FPGA to the memory and the controller itself runs at quarter-rate in the
FPGA i.e. 266.667 MHz.
Figure 2-14 Block Diagram of DDR4 x2 Demonstration

Design Tools

Quartus Prime 18.0.0 Standard Edition

Demonstration Source Code:

Project Directory: Demonstration\RTL_DDR4

Bit Stream: RTL_DDR4.sof

Demonstration Batch File
Demo Batch File Folder: RTL_DDR4 \demo_batch
The demo batch file includes following files:

Batch File: test.bat

FPGA Configuration File: RTL_DDR4.sof

Demonstration Setup
1. Make sure Quartus Prime is installed on the host PC.
2. Connect HAN Pilot Platform to the host PC via USB cable. Install the USB-Blaster II driver if
necessary.
3. Set MSEL[2:0] to 010.
4. Power on the HAN Pilot Platform.
5. Execute the demo batch file “test.bat” under the batch file folder \ RTL_DDR4\demo_batch.
6. Press KEY0 on HAN Pilot Platform to start the verification process. When KEY0 is released,
LED0, LED1 should start blinking. After approximately 2 seconds, LED1 and LED2 should
stop blinking and stay on to indicate the DDR4 (A) and DDR4 (B) have passed the test,
respectively.
Table 2-1 lists the LED indicators.
7. If LED0 or LED1 does not start blinking upon releasing KEY0, it indicates local_cal_success of