Terasic DE10-Agiles, Руководство пользователя

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DE10-Agilex
User Manual 29 www.terasic.com
January 29,
2021
DDR4D_REFCLK_p
166.667
MHz
LVDS PIN_CN38
DDR4 reference
clock for D port
Table 2-12 lists the programming clock generator (Si5340A and for QSFP-DD interface)
control pins, signal names, I/O standard and their corresponding Agilex device pin
numbers.
Table 2-12 Programmable clock generator control pin, Signal Name, I/O standard,
Pin Assignments and Descriptions
Programmable
clock
generator
Schematic
Signal Name
I/O
Standard
Agilex Pin
Number
Description
Si5340A
(U13)
SI5340A_I2C_SCL 1.2V PIN_CV27 I2C bus, connected
with Si5340A
SI5340A_I2C_SDA 1.2V PIN_CR28
SI5340A_LOL 1.2V PIN_CT19
Si5340A loss of
lock, This pin
indicates when the
DSPLL™ is
locked (high) or
out-of-lock (low).
SI5340A_LOS_XAXB 1.2V PIN_CV19
Si5340A loss of
XA/XB signal
SI5340A_RST_n 1.2V PIN_CU28 Si5340A reset signal
SI5340A_OE_n 1.2V PIN_CT29
Si5340A output
enable signal
2.6 DDR4 SO-DIMM
The development board supports four independent banks of DDR4 SDRAM SO-DIMM.
Each DDR4 SODIMM socket is wired to support a maximum capacity of 16GB (Dual
rank) with ECC. Using differential DQS signaling for the DDR4 SDRAM interfaces, it is
capable of running at up to 1333MHz memory clock for a maximum theoretical
bandwidth up to 153.6Gbps. The memory clock of each DDR4 SO-DIMM SDRAM can
be up to 1333MHz (If plug single rank DDR4 SO-DIMM) . Figure 2-16 shows the
connections between the DDR4 SDRAM SO-DIMMs and Agilex FPGA.