Terasic DE1-SoC-MTL2 Скачать руководство пользователя страница 1 | Manualshive

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Содержание DE1-SoC-MTL2

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Страница 2: ...2 2 Block Diagram 10 2 3 ITG Adapter 11 CHAPTER 3 USING DE1 SOC MTL2 13 3 1 Using FPGA 13 3 2 Pin Definition of 2x20 GPIO Connector 13 3 3 Using LCD 15 3 4 Using Terasic Multi touch IP 17 CHAPTER 4 LINUX BSP 20 4 1 Board Support Package 20 4 2 Linux Image Files 21 4 3 Quarts Project 21 4 4 QT Libraries 22 CHAPTER 5 PAINTER DEMONSTRATION 23 5 1 Operation Description 23 5 2 System Description 25 5 3...

Страница 3: ...DE1 SoC MTL2 User Manual 2 www terasic com December 18 2014 CHAPTER 6 APPENDIX 27 6 1 Revision History 27 6 2 Copyright Statement 27 ...

Страница 4: ...A as well as a 5 Point capacitive LCD multimedia color touch panel which natively supports five points multi touch and gestures The all in one embedded solution offered on the DE1 SoC MTL2 in combination of a LCD touch panel and digital image module provides embedded developers the ideal platform for multimedia applications with unparallel processing performance Developers can benefit from the use...

Страница 5: ...n device EPCS128 for the FPGA o On board USB Blaster II normal type B USB connector Memory Devices o 64MB 32Mx16 SDRAM for the FPGA o 1GB 2x256MBx16 DDR3 SDRAM for the HPS o microSD card socket for the HPS Peripherals o Two port USB 2 0 Host ULPI interface with USB type A connector o UART to USB USB Mini B connector o 10 100 1000 Ethernet o PS 2 mouse keyboard o IR emitter receiver o I2C multiplex...

Страница 6: ...ge 0 2 5 V or 0 5V by selecting the RANGE bit in the control register Switches Buttons and LEDs o 5 user keys 4 for the FPGA and 1 for the HPS o 10 user switches for the FPGA o 11 user LEDs 10 for the FPGA and 1 for the HPS o 2 HPS reset buttons HPS_RESET_n and HPS_WARM_RST_n o Six 7 segment displays Sensor o G sensor for the HPS Power o 12V DC input Capacitive LCD Touch Screen o Equipped with an ...

Страница 7: ...B x 480 dot Display mode Normally White Transmissive Dot pitch 0 0642 W x0 1790 H mm Active area 154 08 W x 85 92 H mm Module size 179 4 W x 117 4 H x 7 58 D mm Surface treatment Anti Glare Color arrangement RGB stripe Interface Digital Backlight power consumption 1 674 Typ W Panel power consumption 0 22 Typ W 1 1 2 2 A Ab bo ou ut t t th he e K Ki it t The kit includes everything users need to ru...

Страница 8: ... to perform the power on test are 1 Please make sure the microSD card is inserted to the microSD card socket J11 onboard 2 Set MSEL 4 0 00000 as shown in Figure 1 3 3 Plug in a USB keyboard to the USB host on the DE1 SoC board 4 Plug in the 12V DC power supply to the DE1 SoC board 5 Power on the DE1 SoC board 6 The LXDE Desktop will appear on the LCD display 7 Use the touch screen to select the sy...

Страница 9: ...eating a bootable microSD card Table 1 1 shows the contents of DE1 SoC MTL2 System CD For the system CD of DE1 SoC mainboard users can download it from the link http cd de1 soc terasic com Table 1 1 Contents of DE1 SoC MTL2 System CD Folder Name Description Datasheet Specifications for major components on the touch screen display module Demonstrations FPGA and SoC design examples Manual Including ...

Страница 10: ...O expansion header on DE1 SoC board through an ITG IDE to GPIO adaptor For more information about the DE1 SoC mainboard please refer to the user manual in DE1 SoC System CD which can be download from the link http cd de1 soc terasic com 2 2 1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s Figure 2 1 and Figure 2 2 show photos of DE1 SoC MTL2 It depicts the layout of the board and in...

Страница 11: ... Figure 2 2 DE1 SoC MTL2 bottom view 2 2 2 2 B Bl lo oc ck k D Di ia ag gr ra am m Figure 2 3 shows the block diagram of MTL2 module The IDE connector bridges all the wires from the peripherals to the FPGA through an ITG adapter Figure 2 3 Block diagram of MTL2 ...

Страница 12: ...Terasic FPGA boards 2 2 3 3 I IT TG G A Ad da ap pt te er r The IDE to GPIO ITG adapter is designed to remap IDE pins to GPIO pins C Co om mp po on ne en nt t a an nd d L La ay yo ou ut t Figure 2 5 and Figure 2 6 show the top and bottom view of ITG adapter respectively The J1 connector is used to connect the FPGA board The J2 connector is used to interface with the IDE cable ...

Страница 13: ...DE1 SoC MTL2 User Manual 12 www terasic com December 18 2014 Figure 2 5 ITG adapter top view Figure 2 6 ITG adapter bottom view ...

Страница 14: ...MTL2 is composed of DE1 SoC SoC development board and 7 touch panel daughter card The DE1 SoC SoC development board with the FPGA device is considered as the main part The DE1 SoC user manual and CD are available at http cd de1 soc terasic com 3 3 2 2 P Pi in n D De ef fi in ni it ti io on n o of f 2 2x x2 20 0 G GP PI IO O C Co on nn ne ec ct to or r The 2x20 GPIO female connector directly connec...

Страница 15: ...artus II Pin Numbers Pin Name Direction IO Standard 1 2 MTL_DCLK Output 3 3 V LVTTL 3 4 MTL_R 0 Output 3 3 V LVTTL 5 MTL_R 1 Output 3 3 V LVTTL 6 MTL_R 2 Output 3 3 V LVTTL 7 MTL_R 3 Output 3 3 V LVTTL 8 MTL_R 4 Output 3 3 V LVTTL 9 MTL_R 5 Output 3 3 V LVTTL 10 MTL_R 6 Output 3 3 V LVTTL 11 12 13 MTL_R 7 Output 3 3 V LVTTL 14 MTL_G 0 Output 3 3 V LVTTL 15 MTL_G 1 Output 3 3 V LVTTL 16 MTL_G 2 Out...

Страница 16: ... 3 3 V LVTTL 37 MTL_TOUCH_I2C_SCL Output 3 3 V LVTTL 38 MTL_TOUCH_I2C_SDA Inout 3 3 V LVTTL 39 MTL_TOUCH_INT_n Input 3 3 V LVTTL 40 3 3 3 3 U Us si in ng g L LC CD D The LCD features 800x480 pixel resolution and runs at 33 MHz pixel rate There is no configuration required to drive the LCD The timing specification is defined as in the Table 3 2 Table 3 3 Figure 3 2 and Figure 3 3 Table 3 2 LCD Hori...

Страница 17: ...ecifications Item Symbol Typical Value Unit Min Typ Max Vertical Display Area tvd 480 TH VS period time tv 510 525 650 TH VS pulse width tvpw 1 20 TH VS Blanking tvb 23 23 23 TH HS Front Porch tvfp 7 22 147 TH Figure 3 2 Horizontal input timing waveform Figure 3 3 Vertical input timing waveform ...

Страница 18: ...le 3 4 The IP requires a 50 MHz signal as a reference clock to the iCLK pin and system reset signal to the iRSTN INT_n The signals of I2C_SCLK and I2C_SDAT pins should be connected to the MTL2_TOUCH_INT_n MTL2_TOUCH_I2C_SCL and MTL2_TOUCH_I2C_SDA signals in the 2x20 GPIO header respectively When touch activity occurs the control application should check whether the value of oREG_GESTURE matches a ...

Страница 19: ...2 Output 10 bit X coordinate of second touch point oREG_Y2 Output 9 bit Y coordinate of second touch point oREG_X3 Output 10 bit X coordinate of first touch point oREG_Y3 Output 9 bit Y coordinate of second touch point oREG_X4 Output 10 bit X coordinate of first touch point oREG_Y4 Output 9 bit Y coordinate of second touch point oREG_X5 Output 10 bit X coordinate of first touch point oREG_Y5 Outpu...

Страница 20: ...e 3 5 Gestures and Its IDs Gesture ID hex Move Up 0x10 Move Left 0x14 Move Down 0x18 Move Right 0x1C Zoom In 0x48 Zoom Out 0x49 No Gesture 0x00 Note The Terasic IP Multi touch IP can also be found under the IP folder in the system CD as well as the reference designs ...

Страница 21: ... with touch screen function included The Linux image files are implemented on HPS ARM and the Quartus project is implemented on FPGA Qsys The Linux image files include the pre built Linux system Users can create a Linux bootable microSD card with the image files The Quartus project includes the controller for VGA display and the touch screen controller for touch screen panel The BSP includes not o...

Страница 22: ...m CD which is available from the link http cd de1 soc terasic com Figure 4 2 shows a screenshot of LXDE desktop after booting The LXDE desktop is displayed on the LCD touch panel This image file also includes the QT library and touch screen library To perform these demos users need to double click the icons of the demos on desktop Figure 4 2 Screenshot of LXDE desktop 4 4 3 3 Q Qu ua ar rt ts s P ...

Страница 23: ... I2C protocol The HPS communicate with the FPGA through AXI bridge The components in FPGA are mapped into user memory of the linux system through memory mapped interface Then the user software can access the IPs in FPGA portion The Quartus project is located under the folder Demonstrations SoC_FPGA MTL2_HPS in the DE1 SoC MTL2 system CD 4 4 4 4 Q QT T L Li ib br ra ar ri ie es s Users can develop ...

Страница 24: ...is controlled by the program in Nios II 5 5 1 1 O Op pe er ra at ti io on n D De es sc cr ri ip pt ti io on n Figure 5 1 shows the Graphical User Interface GUI of Painter demo The GUI is classified into four separate areas Painting Area Gesture Indicator Clear Button and Color Palette Users can select a color from the color palette and start painting in the paint area If a gesture is detected the ...

Страница 25: ... December 18 2014 Figure 5 2 shows the single finger painting of canvas area Figure 5 2 Single finger painting Figure 5 3 shows the zoom in gesture Figure 5 3 Zoom in gesture Figure 5 4 5 Point painting of canvas area Figure 5 4 5 Point painting ...

Страница 26: ...nput For multi touch processing When touch activity occurs a I2C Controller IP is used to retrieve serial data from the I2C interface the associated touch information including multi touch gestures and 5 Point touch coordinates can be calculated through the data in NIOS II Note the license for this IP must be installed before compiling the Quartus II project including this encrypted component Figu...

Страница 27: ... Execute DE1_SoC_MTL2_PAINTER bat 6 The painter GUI will show up on the LCD panel 5 4 D De em mo on ns st tr ra at ti io on n S So ou ur rc ce e C Co od de e The locations of this demonstration source code are shown in Table 5 1 Note The project is built under Quartus II v14 0 Both Altera VIP license is required to rebuild the project Table 5 1 Locations of Painter Demonstration Source Code Projec...

Страница 28: ... 18 2014 Chapter 6 Appendix 6 6 1 1 R Re ev vi is si io on n H Hi is st to or ry y Version Change Log V1 0 Initial Version Preliminary 6 6 2 2 C Co op py yr ri ig gh ht t S St ta at te em me en nt t Copyright 2014 Terasic Technologies All rights reserved ...

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