Terasic Altera Cyclone V GX Starter Kit Скачать руководство пользователя страница 1 | Manualshive

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Содержание Altera Cyclone V GX Starter Kit

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Страница 2: ...C 17 2 7 UART USB COMMUNICATION 18 2 8 HDMI TX 19 2 9 HSMC 20 2 10 OVERALL STRUCTURE OF THE C5G CONTROL PANEL 21 CHAPTER 3 USING THE STARTER KIT 23 3 1 CONFIGURATION STATUS AND SETUP 23 3 2 GENERAL US...

Страница 3: ...DDR2 SDRAM RTLTEST 65 CHAPTER 6 NIOS II BASED EXAMPLE CODES 68 6 1 SRAM 68 6 2 UART TO USB CONTROL LED 71 6 3 HDMI TX 75 6 4 TRANSCEIVER HSMC LOOPBACK TEST 83 6 5 AUDIO RECORDING AND PLAYING 84 6 6 MI...

Страница 4: ...lopment board includes hardware such as Arduino Header on board USB Blaster audio and video capabilities and much more In addition an on board HSMC connector with high speed transceivers allows for an...

Страница 5: ...pporting materials including the User Manual Control Panel System Builder reference designs and device datasheets User can download this System CD from the web http c5g terasic com 1 1 3 3 L La ay yo...

Страница 6: ...5 Figure 1 2 Development Board top view Figure 1 3 Development Board bottom view...

Страница 7: ...ontrollers Six 3 125G Transceivers C Co on nf fi ig gu ur ra at ti io on n a an nd d D De eb bu ug g Quad Serial Configuration device EPCQ256 on FPGA On Board USB Blaster Normal type B USB connector M...

Страница 8: ...t CODEC Line in line out and microphone in jacks S Sw wi it tc ch he es s B Bu ut tt to on ns s a an nd d L LE ED Ds s 18 LEDs 10 Slide Switches 4 Debounced Push Buttons 1 CPU reset Push Buttons P Po...

Страница 9: ...connections are made through the Cyclone V GX FPGA device Thus the user can configure the FPGA to implement any system design Figure 1 4 Board Block Diagram 1 1 5 5 G Ge et tt ti in ng g H He el lp p...

Страница 10: ...our host computer and launch the control panel by executing the C5G_ControlPanel exe Specific control circuits should be downloaded to your FPGA board before the control panel can request it to perfor...

Страница 11: ...t port you cannot use Quartus II to download a configuration file into the FPGA until the USB port is closed 7 The Control Panel is now ready for use experience it by setting the ON OFF status for som...

Страница 12: ...yclone V Starter Kit board Figure 2 2 The C5G Control Panel concept The C5G Control Panel can be used to light up LEDs change the values displayed on 7 segment monitor buttons switches status read wri...

Страница 13: ...pl la ay ys s A simple function of the Control Panel is to allow setting the values displayed on LEDs 7 segment displays Choosing the LED tab leads to the window in Figure 2 3 Here you can directly t...

Страница 14: ...y Note that the dots of the 7 SEGs are not enabled on Cyclone V GX Starter Board Figure 2 4 Controlling 7 SEG display The ability to set arbitrary values into simple display devices is not needed in t...

Страница 15: ...d show the status in a graphical user interface It can be used to verify the functionality of the slide switches and push buttons Figure 2 5 Monitoring switches and buttons The ability to check the st...

Страница 16: ...ach the window in Figure 2 6 Figure 2 6 Accessing the LPDDR2 A 16 bit word can be written into the LPDDR2 by entering the address of the desired location specifying the data to be written and pressing...

Страница 17: ...exadecimal values For example a file containing the line 0123456789ABCDEF defines eight 8 bit values 01 23 45 67 89 AB CD EF These values will be loaded consecutively into the memory The Sequential Re...

Страница 18: ...tab leads to the window in Figure 2 7 2 Insert an SD Card to the Cyclone V GX Starter board and then press the Read button to read the SD Card The SD Card s identification specification and file forma...

Страница 19: ...V GX Starter Board The setup is established by connecting a USB cable from the PC to the USB port where the Control Panel communicates to the terminal emulator software on the PC or vice versa The Re...

Страница 20: ...ure 2 9 UART to USB Serial Communication 2 2 8 8 H HD DM MI I T TX X C5G Control Panel provides video pattern function that allows users to output color pattern to HDMI interfaced LCD monitor using th...

Страница 21: ...ach the window shown in Figure 2 11 This function is designed to verify the functionality of the signals located on the HSMC connector Before running the HSMC loopback verification test follow the ins...

Страница 22: ...ware part is implemented in C code the hardware part is implemented in Verilog HDL code with Qsys builder The source code is not available on the C5G System CD To run the Control Panel users should ma...

Страница 23: ...22 Figure 2 12 The block diagram of the C5G control panel...

Страница 24: ...device Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is do...

Страница 25: ...he chain via HSMC connector remove JP2 Jumper open pin1 and pin2 on JP2 to enable the JTAG signal ports on the HSMC connector Figure 3 1 The JTAG chain on Cyclone V GX Starter Kit board Figure 3 2 The...

Страница 26: ...Configure the JTAG programming circuit by setting the RUN PROG slide switch SW11 to the RUN position See Figure 3 4 Connect the supplied USB cable to the USB Blaster port on the Cyclone V GX Starter...

Страница 27: ...artus II Programmer to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then...

Страница 28: ...t This section describes the user I O interface to the FPGA User Defined Push buttons The board includes four user defined push buttons that allow users to interact with the Cyclone V GX device as sh...

Страница 29: ...inputs in a circuit Table 3 2 lists the board references signal names and their corresponding Cyclone V GX device pin numbers Figure 3 7 Connections between the push button and Cyclone V GX FPGA Pushb...

Страница 30: ...pressed 3 3 V PIN_AB24 User Defined Slide Switch There are ten slide switches connected to FPGA on the board See Figure 3 9 These switches are not debounced and are assumed for use as level sensitive...

Страница 31: ...SW8 Slide Switch 8 1 2 V PIN_Y11 SW9 SW9 Slide Switch 9 1 2 V PIN_AE19 User Defined LEDs There are also eighteen user controllable LEDs connected to FPGA on the board Ten red LEDs are situated above t...

Страница 32: ...V PIN_B6 LEDG6 LEDG6 2 5 V PIN_H8 LEDG7 LEDG7 2 5 V PIN_H9 User Defined 7 Segment Displays The FPGA board has four 7 segment displays As indicated in the schematic in Figure 3 11 the seven segments c...

Страница 33: ...nections between the 7 segment display HEX0 and Cyclone V GX FPGA Table 3 5 User 7 segment display Pin Assignments Schematic Signal Names and Functions Board Reference Schematic Signal Name Descriptio...

Страница 34: ...6 HEX2 HEX0_D2 Seven Segment Digit 2 2 Share GPIO24 3 3 V PIN_U20 HEX2 HEX0_D3 Seven Segment Digit 2 3 Share GPIO25 3 3 V PIN_V22 HEX2 HEX0_D4 Seven Segment Digit 2 4 Share GPIO26 3 3 V PIN_V20 HEX2 H...

Страница 35: ...Generator control pins signal names I O standard and their corresponding Cyclone V GX device pin numbers Table 3 6 Clock Source Signal Name Default Frequency Pin Assignments and Functions Source Schem...

Страница 36: ...terface is done using UART USB on board bridge from a FT232R chip and connects to the host using a USB Type B connector For detailed information on how to use the transceiver please refer to the datas...

Страница 37: ...he datasheet which is available on the manufacturer s website or under the Datasheets SRAM folder on the Kit System CD Figure 3 15 shows the related schematics and Table 3 10 lists the SRAM pin assign...

Страница 38: ..._L23 SRAM_D7 Data bus 3 3 V PIN_L24 SRAM_D8 Data bus 3 3 V PIN_H23 SRAM_D9 Data bus 3 3 V PIN_H24 SRAM_D10 Data bus 3 3 V PIN_H22 SRAM_D11 Data bus 3 3 V PIN_J23 SRAM_D12 Data bus 3 3 V PIN_F23 SRAM_D...

Страница 39: ...GX FPGA and LPDDR2 Chip Figure 3 17 LPDDR2 and Cyclone V GX FPGA Table 3 11 LPDDR2 Memory Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Cyclone V...

Страница 40: ..._DQ17 Data bus 1 2 V HSUL PIN_AD17 DDR2LP_DQ18 Data bus 1 2 V HSUL PIN_AC18 DDR2LP_DQ19 Data bus 1 2 V HSUL PIN_AF19 DDR2LP_DQ20 Data bus 1 2 V HSUL PIN_AC17 DDR2LP_DQ21 Data bus 1 2 V HSUL PIN_AB17 D...

Страница 41: ...V HSUL PIN_AF14 DDR2LP_CKE1 Clock Enable 1 Not use 1 2 V HSUL PIN_AE13 DDR2LP_CS_n0 Chip Select 0 1 2 V HSUL PIN_R11 DDR2LP_CS_n1 Chip Select 1 Not use 1 2 V HSUL PIN_T11 DDR2LP_OCT_RZQ ZQ calibration...

Страница 42: ...Functions Schematic Signal Name Description I O Standard Cyclone V GX Pin Number SD_CLK Serial Clock 3 3 V PIN_AB6 SD_CMD Command Response 3 3 V PIN_W8 SD_DAT0 Serial Data 0 3 3 V PIN_U7 SD_DAT1 Seria...

Страница 43: ...signments and signal names relative to the Cyclone V GX device Figure 3 20 Connections between the Cyclone V GX FPGA and HDMI Transmitter Chip Table 3 13 HDMI Pin Assignments Schematic Signal Names an...

Страница 44: ...T Interrupt Signal 1 2 V PIN_T12 I2C_SCL I2C Clock 2 5 V PIN_B7 I2C_SDA I2C Data 2 5 V PIN_G11 3 3 9 9 A Au ud di io o I In nt te er rf fa ac ce e The board provides high quality 24 bit audio via the...

Страница 45: ...development board contains one HSMC connector The HSMC connector provides a mechanism to extend the peripheral set of an FPGA host board by means of add on cards which can address today s high speed...

Страница 46: ...an be found bottom right corner near the HSMC connector The factory default setting is OFF meaning the 12V power won t be available to the daughter boards When users need to connect the daughter board...

Страница 47: ...3 HSMC Signal Bank Diagram Table 3 16 Power Supply of the HSMC Supplied Voltage Max Current Limit 12V 1A 3 3V 1 5A Table 3 17 Pin Assignments for HSMC connector Schematic Signal Name Description I O S...

Страница 48: ...RX bit 3 1 5 V PCML PIN_V2 HSMC_GXB_TX_p0 Transceiver TX bit 0 1 5 V PCML PIN_AE4 HSMC_GXB_TX_p1 Transceiver TX bit 1 1 5 V PCML PIN_AC4 HSMC_GXB_TX_p2 Transceiver TX bit 2 1 5 V PCML PIN_AA4 HSMC_GX...

Страница 49: ...PIN_E16 HSMC_RX _p13 LVDS RX bit 13 or CMOS I O LVDS or 2 5 V PIN_D18 HSMC_RX _p14 LVDS RX bit 14 or CMOS I O LVDS or 2 5 V PIN_E20 HSMC_RX _p15 LVDS RX bit 15 or CMOS I O LVDS or 2 5 V PIN_D21 HSMC_R...

Страница 50: ..._p13 LVDS TX bit 13 or CMOS I O LVDS or 2 5 V PIN_A23 HSMC_TX _p14 LVDS TX bit 14 or CMOS I O LVDS or 2 5 V PIN_C17 HSMC_TX _p15 LVDS TX bit 15 or CMOS I O LVDS or 2 5 V PIN_C19 HSMC_TX _p16 LVDS TX...

Страница 51: ...the I O distribution of the GPIO connector The maximum power consumption of the daughter card that connects to GPIO port is shown in Table 3 18 Table 3 19 shows all the pin assignments of the GPIO co...

Страница 52: ...us Signal Name Description I O Standard Cyclone V GX Pin Number GPIO0 GPIO DATA 0 Dedicated Clock Input 3 3 V PIN_T21 GPIO1 GPIO DATA 1 3 3 V PIN_D26 GPIO2 GPIO DATA 2 Dedicated Clock Input 3 3 V PIN_...

Страница 53: ...O26 HEX2_D4 GPIO DATA 26 3 3 V PIN_V20 GPIO27 HEX2_D5 GPIO DATA 27 3 3 V PIN_W21 GPIO28 HEX2_D6 GPIO DATA 28 3 3 V PIN_W20 GPIO29 HEX3_D0 GPIO DATA 29 3 3 V PIN_Y24 GPIO30 HEX3_D1 GPIO DATA 30 3 3 V P...

Страница 54: ...N_E26 Arduino_IO1 Arduino IO1 3 3 V PIN_K26 Arduino_IO2 Arduino IO2 3 3 V PIN_M26 Arduino_IO3 Arduino IO3 3 3 V PIN_M21 Arduino_IO4 Arduino IO4 3 3 V PIN_P20 Arduino_IO5 Arduino IO5 3 3 V PIN_T22 Ardu...

Страница 55: ...The internal conversion clock allows the external serial output data clock SCK to operate at any frequency up to 40MHz The LTC2308 is controlled via a serial SPI bus interface which is connected to p...

Страница 56: ...and Functions Schematic Signal Name Description I O Standard Cyclone V GX Pin Number ADC_CONVST Conversion Start 1 2 V PIN_AB22 ADC_SCK Serial Data Clock 1 2 V PIN_AA21 ADC_SDI Serial Data Input FPGA...

Страница 57: ...top level design file or place pin assignments The common mistakes that users encounter are the following 1 Board damage due to wrong pin bank voltage assignments 2 Board malfunction caused by wrong...

Страница 58: ...4 3 3 U Us si in ng g C C5 5G G S Sy ys st te em m B Bu ui il ld de er r This section provides the detailed procedures on how the C5G System Builder is used Install and launch the C5G System Builder...

Страница 59: ...lder window Input Project Name Input project name as show in Figure 4 3 Project Name Type in an appropriate name here it will automatically be assigned as the name of your top level design entity Figu...

Страница 60: ...Group GPIO Expansion Users can connect GPIO daughter cards onto the GPIO connector located on the development board As shown in Figure 4 4 select the daughter card you wish to add to your design unde...

Страница 61: ...ino daughter cards onto the Arduino connector located on the development board As shown in Figure 4 6 select the Arduino Digital and check the ADC item The System Builder will automatically generate t...

Страница 62: ...the development board As shown in Figure 4 7 select the daughter card you wish to add to your design under the appropriate HSMC connector to which the daughter card is connected The System Builder wi...

Страница 63: ...esign Users may leave this field empty Project Setting Management The C5G System Builder also provides functions to restore default setting loading a setting and saving users board configuration file...

Страница 64: ...y C5G System Builder No Filename Description 1 Project name v Top level Verilog HDL file for Quartus II 2 Project name qpf Quartus II Project File 3 Project name qsf Quartus II Setting File 4 Project...

Страница 65: ...f Demonstration Setup and Instructions Power on the C5G board You should now be able to observe that LEDs and 7 SEGs are flashing Press CPU_RESET_n to make LEDs and 7 SEGs all light on Optionally conn...

Страница 66: ...st t This demonstration presents a memory test function on the bank of LPDDR2 SDRAM on the C5G board The memory size of the LPDDR2 SDRAM bank is 512MB Function Block Diagram Figure 5 1 shows the funct...

Страница 67: ...e C5G_LPDDR2_RTL_Test sof Demonstration Setup Make sure Quartus II is installed on your PC Connect the USB cable to the USB Blaster connector J10 on the C5G board and host PC Power on the C5G board Ex...

Страница 68: ...67 Press KEY0 again to regenerate the test control signals for a repeat test Table 5 1 LED Indicators Table 5 2NAME Description LEDG0 Reset LEDG1 If light LPDDR2 test pass LEDG2 Blinks...

Страница 69: ...of the associated files can be found in the Demonstrations folder on the System CD 6 6 1 1 S SR RA AM M This demonstration presents a memory test function of SRAM on the C5G board The memory size of t...

Страница 70: ...verification The program will show progress in JTAG Terminal when writing reading data to from the SRAM When verification process is completed the result is displayed in the JTAG Terminal Design Tool...

Страница 71: ...our PC Power on the C5G board Use USB cable to connect PC and the C5G board J10 and install USB Blaster driver if necessary Execute the demo batch file C5G_SRAM bat for USB Blaster under the batch fil...

Страница 72: ...ormat Developers can use a usb cable rather than a RS232 cable to make the FPGA communicate with computer In this demonstration we will show you how to control the leds by sending command on computer...

Страница 73: ...rtus Project directory C5G_UART Nios II Eclipse C5G_UART Software Nios II Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned...

Страница 74: ...an unrecognized USB Serial Port as shown in Figure 6 4 you should install the UART to USB driver before you run the demonstration Figure 6 4 Unrecognized USB Serial Port on PC To install UART_TO_USB d...

Страница 75: ...ned Com Port number On PC Open the putty software and setup the parameter as shown in Figure 6 5 and click open button to open the terminal Figure 6 6 putty terminal setup Make sure Quartus II and Nio...

Страница 76: ...erence is composed of two parts the hardware design and the software control program A set of pre built video patterns will be sent out through the HDMI interface and presented on the LCD monitor as t...

Страница 77: ...rol allows users to switch current display mode alternatively via the KEY1 push button Table 6 1 Build in Display Modes of the HDMI TX Demonstration Pattern ID Video Format PCLK MHZ 0 640x480 60P 25 1...

Страница 78: ...rent HPD and monitor sense state reported in one of the encoder registers If both HPD and monitor sense are confirmed to be asserted the ISR will try to power up the encoder chip and program it to int...

Страница 79: ...ab to activate the Generation property page Hit the Generate button below the page to regenerate the SOPC file named as HDMI_QSYS sopcinfo which would be used to update the Nios II BSP project mention...

Страница 80: ...on binaries are located at the C5G_HDMI_VPG demo_batch folder accompanied with a set of tools in the form of command line batch file To make a quick start users could follow the listed approaches belo...

Страница 81: ...to interact with the on board HDMI encoder Auto Hot Plug Detection The demonstration implements an interrupt driven hot plug detection mechanism which will automatically power on the encoder chip whe...

Страница 82: ...zation process and start to sync with the HDMI encoder Video Pattern Switching Pressing the on board push button KEY1 can switch the current display mode alternatively between the build in formats lis...

Страница 83: ...hat non CEA 861 D input formats may not be reported in a fully correct way r addr Read the register value of the HDMI encoder at address addr where addr is a 2 digit hexadecimal number w addr data Wri...

Страница 84: ...artus II 13 0 Nios II Eclipse 13 0 Demonstration Source Code Quartus Project directory C5G_XCVR_LOOPBACK Nios II Eclipse C5G_XCVR_LOOPBACK Software Nios II Project Compilation Before you attempt to co...

Страница 85: ...y yi in ng g This demonstration shows how to implement an audio recorder and player using the C5G board with the built in Audio CODEC chip This demonstration is developed based on Qsys and Eclipse Fig...

Страница 86: ...art includes all the other blocks The AUDIO Controller is a user defined Qsys component It is designed to send audio data to the audio chip or receive audio data from the audio chip The audio chip is...

Страница 87: ...he C5G board Connect a speaker or headset to LINE OUT port on the C5G board Load the bit stream into FPGA note 1 Load the Software Execution File into FPGA note 1 Configure audio with the Slide switch...

Страница 88: ...C5G board provides the hardware and software needed for Micro SD Card access In this demonstration we will show how to browse files stored in the root directory of an SD Card and how to read the file...

Страница 89: ...users can open a specified file and read the contents of the file The main block implements main control of this demonstration When the program is executed it detects whether an Micro SD Card is inser...

Страница 90: ...C5G_SD_DEMO Software Nios II Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project men...

Страница 91: ...B Blaster driver if necessary Execute the demo batch file C5G_SD_DEMO bat for USB Blaster II under the batch file folder C5G_SD_DEMO demo_batch After Nios II program is downloaded and executed success...

Страница 92: ...s CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Analog Devices SSM2603 audio CODEC to play the music Figure 6 20 shows the hardwar...

Страница 93: ...s FAT16 FAT32 file system for reading wave files that is stored in the SD Card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for extracting...

Страница 94: ...e SD Card and then writes the data to DAC FIFO in the Audio Controller Before writing the data to the FIFO the program will verify if the FIFO is full The design also mixes the audio signal from the m...

Страница 95: ...ctory of the Micro SD Card The provided wave files must have a sample rate of either 96K 48K 44 1K 32K or 8K In addition the wave files must be stereo and 16 bits per channel Connect a headset or spea...

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