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ADC-FMC User Manual

7

www.terasic.com

April 24, 2020

Figure 2-1 Top view of the ADC-FMC Daughter Card

The bottom view of the ADC-FMC is shown in

. It depicts the layout and indicates the

locations of connectors and key components.

Figure 2-2 Bottom view of the ADC-FMC Daughter Card

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Содержание ADC-FMC

Страница 1: ......

Страница 2: ...C FMC 6 2 1 Features 6 2 2 Component and Layout 6 2 3 Block Diagram 8 Chapter 3 Using the ADC FMC 9 3 1 Pin Definition of FMC Connector 9 3 2 Using the ADC Chip AD9648BCPZ 125 13 3 3 Select reference...

Страница 3: ...come from a FPGA via the on board FMC connector or from an external clock source via the on board SMA connector Note the FPGA main board FMC interface will support VADJ 1 8V to work with ADC FMC 1 1 1...

Страница 4: ...FMC daughter card has reserved two screw holes as shown in Figure 1 2 Users can use the screws copper pillars and nuts that come with the ADC FMC to make the ADC FMC secure on the FPGA mainboard as s...

Страница 5: ...TR5 and A5SoC FPGA boards The ADC FMC is powered from FPGA mainboard It is not necessary to connect a power adapter to the ADC FMC There are four ADC channels on the ADC FMC board Full pin count FMC...

Страница 6: ...l 24 2020 Figure 1 5 ADC FMC with A5SoC 1 1 4 4 G Ge et tt ti in ng g H He el lp p For Technical Support Terasic s Contact Information is listed below Office Hours 9 00 a m to 6 00 p m GMT 8 Telephone...

Страница 7: ...o use four ADC channels the mainboard s FMC connect must support 1 8V full pin count 2 2 1 1 F Fe ea at tu ur re es s The key features of this module are listed below Four high speed ADC ports Connect...

Страница 8: ...4 2020 Figure 2 1 Top view of the ADC FMC Daughter Card The bottom view of the ADC FMC is shown in Figure 2 2 It depicts the layout and indicates the locations of connectors and key components Figure...

Страница 9: ...he reference clock of the ADC chip can come from on board clock generator Si5340B FPGA main board via FMC connector External clock source via SMA connectors The selection of clock sources is determine...

Страница 10: ...generator hardware in the board Note when using this board remember FMC VCCADJ of main board must be set to 1 8V 3 3 1 1 P Pi in n D De ef fi in ni it ti io on n o of f F FM MC C C Co on nn ne ec ct...

Страница 11: ...al Name FMC Pin No Description Direction IO Standard ADC_A_D0 H28 First ADC Port A Data0 input VCCADJ ADC_A_D1 G36 First ADC Port A Data1 input VCCADJ ADC_A_D2 H31 First ADC Port A Data2 input VCCADJ...

Страница 12: ...input VCCADJ ADC_B_D10 G25 First ADC Port B Data10 input VCCADJ ADC_B_D11 H25 First ADC Port B Data11 input VCCADJ ADC_B_D12 D26 First ADC Port B Data12 input VCCADJ ADC_B_D13 G24 First ADC Port B Dat...

Страница 13: ...ort B Data4 input VCCADJ ADC_D_D5 E24 Second ADC Port B Data5 input VCCADJ ADC_D_D6 E25 Second ADC Port B Data6 input VCCADJ ADC_D_D7 E21 Second ADC Port B Data7 input VCCADJ ADC_D_D8 F19 Second ADC P...

Страница 14: ...voltage should be 0 2 0 Voltage Figure 3 4 Differential Transformer Coupled Configuration Figure 3 5 shows the function block diagram of the ADC chip Developers need to provide a reference clock to t...

Страница 15: ...amic select the clock source via the ADC1_CK_S0 S1 pins for the first ADC chip and the ADC2_CK_S0 S1 pins for the second ADC chip as shown in Table 3 2 Table 3 2 Clock Source Selection S1 S0 Clock Sou...

Страница 16: ...oltage range of clock input to SMA connector When switches are off the input clock voltage is expected to 3 3V When switches are on the input clock voltage is expected to 2 5V If FPGA clock source is...

Страница 17: ...store the retrieved digitalized values from four ADC Channels Data output of each ADC channel has an associated FIFO to store the data Each FIFO is configured as separated input clock and output cloc...

Страница 18: ...r rd d This section shows how to setup the demo on the Terasic TR5 FPGA Board TR5 FMC A connector is used to connect the ADC FMC board in this demo User also can use FMC D connector on TR5 FMC B and F...

Страница 19: ...ster II USB port J6 of the TR5 to the USB port of host PC with a Mini USB cable 5 Power on the TR5 FPGA board 6 Make sure Quartus Prime and USB Blaster II driver has been installed on the host PC 7 Co...

Страница 20: ...a ai in nb bo oa ar rd d This section shows how to setup the demo on the Intel A5SoC FPGA Board A5SoC FMC A connector is used to connect the ADC FMC board in this demo User also can use FMC B connecto...

Страница 21: ...ndard or set SW1 SW2 as ON if the output signal is 2 5V 3 Make sure the FMC VAR J6 is set to 1 8V as shown in Figure 4 7 4 Connect the USB Blaster II USB port J50 of the A5SoC to the USB port of host...

Страница 22: ...asic com April 24 2020 Figure 4 8 SWITCH 1 0 on A5SoC Project Source Code The source code of Quartus project for the ADC demo with the A5SoC board is available in the Demonstrations A5SoC_ADC FMCA fol...

Страница 23: ...n H Hi is st to or ry y Version Date Change Log V1 0 10 24 2018 Initial Version Preliminary V1 1 07 18 2019 Update for rev B Adding buffer V1 2 04 24 2020 Modify Figure 3 1 3 2 3 3 and Table 3 1 5 5...

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