WE310F5-X IP2WiFi Legacy AT Command Reference Guide
80664ST11079A Rev. 3
Page 15 of 79
2021-10-25
Not Subject to NDA
Operation
Escape Sequence
Description
SPI-NON DMA, SPI-DMA) when serial host sends data to
any invalid socket.
Note/Tip: The contents of < > are either a byte or byte stream, except
for <ESC>; literals outside brackets are ASCII characters.
4.3.1.
Bulk Data Tx and Rx
In Bulk Data Mode, data transfers are managed using escape sequences (ESC Z, ESC Y
and ESC y). Each escape sequence starts with the Escape <ESC> key (ASCII character 27
(0x1B)). Encoding is used for both transmitted and received data. Enable bulk data by
using command “AT+BDATA=”
. For more details, see Bulk Data Handling, page 156
4.3.2.
Hardware Flow Control
The Hardware Flow Control is a handshake mechanism between the Serial host and S2W
Application on UART interface, using two additional CTS and RTS connections. This
feature prevents the UART hardware FIFO overflow on S2W Application due to high speed
data transmission from/to the S2W Application. If hardware flow control is enabled, an
RTS/CTS handshake will occur between the serial host and the WE310F5-X node. This is
a hardware feature and available only for UART interface.
The S2W Application uses both CTS and RTS signals as “low” to indicate the readiness to
send or receive data from serial host.
Serial Data Handling
The Serial Data Handler receives and transmits data to and from the hardware serial
controller. Data read from the serial port is passed to:
1.
The command processor in command mode
2.
The Tx data handler in data mode
3.
The auto connection mode processor for data transfer in auto connection mode
Then Data is transferred on the serial port from:
1.
The command processor in order to output responses to commands
2.
The Tx data handler in order to output incoming packets
3.
The Rx data handler in order to output incoming packets
