LM940 Hardware Design Guide
1VV0301352 Rev. 18
Page 32 of 75
2022-01-04
Not Subject to NDA
6.
DIGITAL SECTION
Logic Levels
Unless otherwise specified, all the interface circuits of the LM940 are 1.8V CMOS logic.
Only USIM interfaces are capable of dual voltage I/O.
The following tables show the logic level specifications used in the LM940 interface
circuits. The data specified in the tables below is valid throughout all drive strengths and
the entire temperature ranges.
Warning:
Do not connect LM940’s digital logic signal di
rectly to
OEM’s digital logic signal with a level higher than 2.3V for 1.8V CMOS
signals.
6.1.1.
1.8V Pins
–
Absolute Maximum Ratings
Absolute Maximum Ratings
–
Not Functional
Parameter
Min
Max
Input level on any digital pin when on
--
+2.16V
Input voltage on analog pins when on
--
+2.16 V
Table 21: Absolute Maximum Ratings
–
1.8V Pins
6.1.2.
1.8V Standard GPIOs
Parameter
Min
Max
Unit
Comment
VIH
Input high level
1.17V
2.1V
[V]
VIL
Input low level
-0.3V
0.63V
[V]
VOH
Output high level
1.35V
1.8V
[V]
VOL
Output low level
0V
0.45V
[V]
IIL
Low-level input
leakage current
-1
--
[uA]
No pull-up
IIH
High-level input
leakage current
--
1
[uA]
No pull-down
IILPU
Low-level input
leakage current
-97.5
-27.5
[uA]
With pull-up
IIHPD
High-level input
leakage current
27.5
97.5
[uA]
With pull-down
CI/o
I/O capacitance
--
5
[pF]
Table 22: Operating Range
–
Interface Levels (1.8V CMOS)