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17-2000 C 
2020-09-17

30(50)

ADQ8-8C Manual

17-2000 C 2020-09-17

30(50)

4.13.1 Distributing trigger 

The trigger is distributed to the boards via the SYNC input and output. The trigger distribution is daisy 
chained, so there is no limit to the number of boards. The cable in 

Figure 21

 from SYNCO to SYNCI is 

the trigger distribution. 

4.13.2 Clock reference 

Use the clock reference distribution in the backplane of the chassis for phase alignment of the digitizers 
in the system. 

4.13.3 High precision trigger on analog input 

The source for the trigger can be any available trigger. If one of the analog inputs is used as a high pre-
cision input, the trigger timing can be computed to 25 ps trigger precision. 

4.13.4 Calibration 

To reach the trigger accuracy of 200 ps for the entire chassis installation, the system has to be cali-
brated in the factory 

[5]

. 

Содержание ADQ8-8C

Страница 1: ...om Regional sales offices www spdevices com contact Manual ADQ8 8C This manual describes how to get the full potential out of Teledyne SP Devices digitizer ADQ8 8C The manual includes these steps Set...

Страница 2: ...Timestamp 14 4 4 1 Timestamp definitions 14 4 4 2 Timestamp reset 14 4 5 Blocking triggers for synchronization 16 4 5 1 Function overview 16 4 5 2 Block triggers once 18 4 5 3 Windowing triggers 18 4...

Страница 3: ...erator 35 5 9 External clock 35 5 10 Clock reference output 35 5 11 Sample skip 35 6 GPIO 36 6 1 GPIO on TRIG connector 36 6 2 ADQ8 8C PXIe GPIO on SYNC connectors 37 6 3 ADQ8 8C MTCA GPIO on SYNC con...

Страница 4: ...8C Manual 17 2000 C 2020 09 17 4 50 8 1 PCI Express interface 48 8 2 Using several units 48 8 2 1 Using several digitizers from a single application 48 8 2 2 Using several digitizers from a several a...

Страница 5: ...ing 1 2 1 Data format The ADC components of ADQ8 8C has 10 bits resolution while the data format inside the ADQ8 8C and out to the host PC is 16 bits The 16 bits from the ADCs are MSB aligned in this...

Страница 6: ...different clock rates The sampling of the analog signal is done on the sampling clock of the ADC see Section 1 2 4 The external trigger input has a trigger clock which is higher than the sample clock...

Страница 7: ...log input signal can vary from 250 mV to 250 mV and the range can be moved from 0 mV 500 mV to 500 mV 0 mV by the DC offset feature Section 2 4 The maximum digital code 2 15 represents an analog signa...

Страница 8: ...o These blocks are linked as in Figure 2 Digitizer Studio is documented in 5 BLOCK DESCRIPTION REF a Analog front end Setting up analog input parameters digital signal transformation 2 b DBS Digital B...

Страница 9: ...e form factor The analog input impedance can be set to 50 or 1 M MTCA 4 form factor input is impedance is fixed 50 to GND SetInputImpedance 2 2 b On ADQ8 8C VG the gain can be set in a discrete number...

Страница 10: ...e voltage level DC_OFF SET_ANALOG use DC_OFFSET_CODE round DC_OFFSET_ANALOG ACTUAL_ANALOG_RANGE 2 2 15 6 Since the digitizer has higher resolution than the intrinsic accuracy of the DC offset generato...

Страница 11: ...ally locks the baseline to a user defined value Note that DBS is off at power up DBS has to be activated by the user s application software The time when DBS is activated is important To get a good in...

Страница 12: ...ger input on front panel connector SYNC 4 8 2 h Select which type of trigger to activate SetTriggerMode i The trigger blocking function controls the flow of triggers to the acquisition engine SetupTri...

Страница 13: ...data record is controlled by the parameters pretrigger and trigger delay The pretrigger buffer enables capturing data prior to the trigger event Figure 5 Use the command Set PreTrigSamples to define...

Страница 14: ...e running the timestamp counter also free run ning See Section 5 for all details about the clock system of digitizer The timestamp counter measures the time from a reference time point to the trigger...

Страница 15: ..._OF_RECORD TIME_STAMP_REFERENCE 3 The third method is to apply an external trigger to reset the timestamp reset Figure 7 This method has the possibility to synchronize several boards to full precision...

Страница 16: ...ger blocking and the timestamp reset the timestamp is aligned to the start of the acquisition The trig ger blocker source can be most available trigger sources Figure 8 a b c Note the order of the co...

Страница 17: ...f This signal is ignored as the trigger blocker is not armed g Select trigger source SetTriggerMode h Start receiving triggers Note that triggers are still blocked ArmTrigger i The unblocking of trig...

Страница 18: ...signal is a point trigger and a sync signal is a line trigger 4 5 4 Gating and windowing triggers The gate mode for blocking triggers is illustrated in Figure 8 l The length of the window where trig...

Страница 19: ...The RMS value of such a process is TRIGGER_CLOCK_PERIOD sqrt 12 The highest resolution is achieved with an external trigger connected to the TRIG connector ADQ8 8C has a trigger clock at 4 GSPS TRIGGE...

Страница 20: ...the timestamp information Section 4 4 The position of the first sample is rounded up from the trigger position The parameter RECORD_START tells where the trigger was Referring to Figure 11 the RECORD_...

Страница 21: ...to the system in the following ways The input impedance can be set in 50 default or high impedance 500 mode see Section 4 8 3 Configure the threshold level Set the trigger edge to rising or falling to...

Страница 22: ...c impedance of 50 This setup results in an optimal high frequency response and low reflections which is important for precise timing DESCRIPTION USER COMMAND REF a The input is available on an SMA con...

Страница 23: ...network to handle the reflections If the trigger is periodic reflections are less critical and can be handled 4 9 External trigger in the backplane 4 9 1 PXIe interface There are an external trigger i...

Страница 24: ...D REF a Backplane Trigger bus and DSTAR connections b Set direction for each port in the backplane SetDirectionPXI c Output Select output port for trigger output signal SetupTriggerOutput 4 12 d Outpu...

Страница 25: ...s illustrated DESCRIPTION USER COMMAND REF a Backplane MLVDS bus b Set direction for each port in the backplane SetDirectionMLVDS c Output Select output port for trigger output SetupTriggerOutput 4 12...

Страница 26: ...ACTUAL_ANALOG_RANGE 2 2 15 12 4 10 3 Controlling noise sensitivity The level trigger is sensitive to noise since it can detect a step as small as one digital code This can cause unwanted triggering Th...

Страница 27: ...first part selects the source of the trigger output signal The second part selects the physical output port for the trigger output signal Note that the trigger output is the same physical TRIG connect...

Страница 28: ...izer with the internal trigger may be done in two ways inter nally Figure 19 and externally Figure 20 The internal connection is preferred when the trigger is only used for triggering the digitizer Th...

Страница 29: ...iagram with 2 synchronized boards DESCRIPTION USER COMMAND REF a Internal trigger generator SetInternalTriggerPeriod 4 11 b Select internal trigger as output SetupTriggerOutput 4 12 c The trigger outp...

Страница 30: ...tion 4 13 2 Clock reference Use the clock reference distribution in the backplane of the chassis for phase alignment of the digitizers in the system 4 13 3 High precision trigger on analog input The s...

Страница 31: ...ource in the primary unit This may be an analog channel using level trigger or any other trigger source DaisyChainSetTriggerSource DaisyChainSetupLevelTrigger c The trigger signal is synchronized to t...

Страница 32: ...arallel to maintain the throughput The Data Clock is also synchronized to the clock reference Finally the host PC interface also operate on a different clock The PCIe system clock is provided from the...

Страница 33: ...MCX connector drives the selected clock reference source to enable synchronization of other equipment EnableClockRefOut 5 3 5 10 c The backplane clocks are available for synchronization d Select which...

Страница 34: ...ccuracy VCTCXO at 10 MHz 5 6 External clock reference The free running internal clock reference of the digitizer offers high precision and is suitable for most measurements However for some applicatio...

Страница 35: ...A D converters The data and trigger clocks are also generated by this clock generator 5 9 External clock If the system is designed with an external high quality signal it may be used for clocking the...

Страница 36: ...in the block dia gram in Figure 26 DESCRIPTION USER COMMAND REF a The external pin is automatically connected to the activated function 6 4 b The GPIO input function always reads the state of the pin...

Страница 37: ...rnal device with GPIO 1 Connect a cable from the TRIG connector to the external device 2 SetTriggerMode external trigger This will activate the trigger module to listen to TRIG 3 SetDirectionGPIOPort...

Страница 38: ...0 09 17 38 50 ADQ8 8C Manual 17 2000 C 2020 09 17 38 50 6 6 GPIO in ADQ Development Kit The GPIO signals from TRIG and SYNC are available in the ADQ Development Kit for real time interac tion with the...

Страница 39: ...e memory is available for that channel The data memory is also shared between data and headers Table 3 A header contains information about the data record for example timestamp and channel number The...

Страница 40: ...plit into cir cular buffers where one buffer can hold one record Data is then written constantly into this buffer until the trigger event arrives After the trigger event Record_length Pretrigger_sampl...

Страница 41: ...the digitizer prepares the DRAM for receiving the next record The re arm time is thus a hardware related fixed timing during which the digitizer cannot record The scheduling of triggers depends on the...

Страница 42: ...ition and after that requests the data This is the straight forward method if the total amount of data is less than the data buffer size Section 7 2 that is it can be stored in the buffer of the digit...

Страница 43: ...FO on the ADQ d The DMA transfers data to the PC when requested by the user e Kernel buffers in the host PC receives the data from the digitizer f The ADQAPI receives incoming data and do necessary pr...

Страница 44: ...f buffers one for header information and one for data The header is always 40 bytes per record and the content is described in Section 7 9 The data buffer size is depending on the amount of data in ea...

Страница 45: ...tional information about e g the experiment is added to the header c Header and data is analyzed in real time and only requested parameters are stored 7 9 Figure 35 Data flow through the system PARAME...

Страница 46: ...ombinations are available for ADQ Development Kit users to create artificial channels 7 9 6 Record number The Record number is counting the number of records captured from the power up of the digitize...

Страница 47: ...offset b Digital offset calibration c Digital baseline stabilizer that dynamically adjust baseline to zero That is adjust the offset Under range has already occurred prior to this stage d Acquisition...

Страница 48: ...ch software command contains a pointer to the control unit for all ADQ digitizers and an instance number that points out the current ADQ To identify a specific unit read the serial number GetBoardSeri...

Страница 49: ...17 49 50 9 REFERENCES 1 17 1997 ADQ8 8C Datasheet 2 14 1351 ADQAPI Reference guide 3 08 0214 ADQAPI User guide 4 18 2059 ADQUpdater user guide 5 20 2382 Digitizer Studio manual 6 19 2246 ADQ8 Daisy Ch...

Страница 50: ...ntities other than Teledyne SP Devices The warranty of replacement products shall terminate with the warranty of the product Buyer shall not return any products for any reason without the prior writte...

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