Teledyne Lecroy PCIe External Cable 3.0 to PCIe Slot Adapter, Руководство пользователя и краткое руководство по началу работы

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3
Connections
.
*
Notes: For J6 and J3/J4: PCIe Reference Clock is not forwarded through the PCIe External Cable 3.0.
Other sideband signals from slot connector such as PERST#, WAKE#, CLKREQ# are not forwarded through the external cable
interface. Outputs are provided in the adapter for debug purposes.
Access to I
2
C Bus
The I
2
C bus is connected from the PCIe Bus card slot to the PCIe External Cable 3.0 to PCIe Slot Adapter
connector J22: Port 0 and J16.
J16 provides access to I
2
C/SMBus signals from the PCIe slot for other I
2
C analysis equipment. See
Table 2
below,
for the I
2
C connections on J16.
PCIe External Cable 3.0 to PCIe Slot Adapter: Interconnection Overview
SW1: PCIe Link
Width Selection.
See settings

Table 1
below.
Host PCIe Card Slot
J16: I
2
C Interface
See
Table 2
below.
J24: Port 3
CH[12-15]
J24: Port 2
CH[8-11]
J22: Port 1
CH[4-7]
J22: Port 0
CH[0-3]
PCIe External Cable 3.0 Test Points:

See
Table 5
below.
J3/J4: PCIe
RefClk to DUT.
MMCX Differential
Output.*
J6: PCIe
RefClk to DUT*
J8: PCIe Bus
Reserved signals.
See
Table 4
below.
J42: See PCIe
Bus Side band
signals see

Table 3
below.
PCIe

External
Cable 3.0

Interface