Tektronix VX4802, Руководство пользователя

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Appendix E: Performance Verification
A–32
VX4802
c. Set the VX4801 to assert the even byte external tri-state signals to the
VX4802 and verify a response of 00FF00FF00FF00FF00FF..:
&'
!(%' !
&'
!(%' !
!%
(Observe: response of 00FF00FF00FF00FF00FF..)
d. Set the VX4801 to assert the odd byte external tri-state signals to the
VX4802 and then set the VX4802 for the even bytes to be inputs, for the
odd bytes to be outputs with a Load Output value of 00, and for external
tri-state ETS0 to be enabled for bytes 1 and 3. Finally, verify a response
of FF00FF00FF00FF00FF00 (odd bytes tri-stated):
&'
!(%' !
&'
!(%' %" ! # '!
!(%' !
!%
(Observe: response of FF00FF00FF00FF00FF00..)
This test sequence verifies that data can be transferred to and from the VX4802
using the four handshake signal lines Data Ready (DRD), Data Acknowledge
(DAK), Ready for Data (RFD), and Data Available (DAV).
NOTE . Typing errors will result in a VX4802 error condition which must be
cleared before subsequent commands will be recognized. If at any time you
suspect that an error condition exists, send an error query and read the result
before continuing with the test sequence
!(%' $ % !% %
.
Equipment
Requirements Loop-back assembly (item 2)
Prerequisites All prerequisites listed on page A–22
1. Connect the loop-back assembly as shown in Figure 4.
Check Handshake
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