Tektronix RG 501, Инструкция по эксплуатации

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Pin
13,Bright Baseline
Control
14,+ Gate Out
1 6,Power Supply
Pin
I
,Sweep Gate In
2.0scillation
Suppressor
3,Ground
4.Delayed Gate Out
S.Not Used
6.Ramp Length
7.Power Supply
a.output
9.Timing Current
Summing Node
10.Substrate
Timing Circuits
Circuit Oescription-RG 501
TABLE 5-1
(cont)
Function
Current into pin (logical 1 for �20 ns keeps pin 12 at ground, holding bright
baseline off. Baseline remains off lor one timing period after current level is removed. No input
(logical 0) allows bright baseline to function (see pin 12).
Provides a +5
V
(logic 1) source through R40 during ramp runup, driving current into pin 1 of the
Miller Integrator. Logic 0 ends ramp.
Provides
Ver:.
of -1-5
V.
TABLE
5-2
Miller Integrator U50
Function
Current into pin 1 results in a linear voltage ramp at pin a.
Connects discrete components to prevent oscillation of the integrator.
Provides a reference ground.
Provides reset logic to pin 1. U30 when output level on pin
a
reaches the level set on pin 6 by RSO.
Held at logic 1 .
Provides the dc reference level for Ihe internal comparator to set up "end of ramp" logic.
Provides
Vee
of
-1-15
volls.
Produces a linear voltage ramp out when current is gated inlo pin 1 . Ramp is positive-going with an
amplitude of approximately 0 to
g
volts.
Connects timing components which determine the ramp rate.
... -13 rnA from R42.
Output Amplifier
SSO, RAMP DURATION. connects liming capacitors
across pins
8
and 9 of
usa
and connects holdoff timing
components to pin 1 1 of U30. With DURATION
MUL TIPUER R56 at
Xl
(fully CW), RSS is the common RT
for all the switched timing positions. RSO,
Xl
Ramp
Length, establishes the dc reference level al pin 6 of USO
for "end of ramp" logic, When RS6 is fully ccw, R63
calibrates the ramp for a
X I I
value .
A positive-going ramp of about 9 V is fed into the non­
inverting input of an operational amplifier formed by
Q70A. 070B, and
082.
A700ffsets the ramp-start potential
at the positive input of the operational amplifier. providing
adjustment for a zero-volt starting point of the output
signal. Closed-loop gain 01 the stage is established by the
ratio of A74 to R7S
. R7S feeds Iheoutputsignal back 10 the
Inverting input, the base of 0708, AaS, RAMP
@ 5-3