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Status and Event Reporting
AWG710 Arbitrary Waveform Generator Programmer Manual
3-3
This block is used to report power on/off, command error, and command
execution status.
The block has two registers: the Standard Event Status Register (SESR) and the
Event Status Enable Register (ESER). Refer to the Standard/Event Status Block
shown at the bottom of Figure 3–1 on page 3–2.
The SESR is an eight-bit status register. When an error or other type of event
occurs on the instrument, the corresponding bit is set. You cannot write to this
register. The ESER is an eight-bit enable register that masks the SESR. You can
set this mask, and take AND with the SESR to determine whether or not the
ESB bit in the Status Byte Register (SBR) should be set. Refer to Event Status
Enable Register (ESER) on page 3–8, and Standard Event Status Register
(SESR) on page 3–6, for the contents of these registers.
This block is used to report on the status of several operations being executed by
the waveform generator.
The block is made up of three registers: the Operation Condition Register
(OCR), the Operation Event Register (OEVR) and the Operation Enable Register
(OENR). Refer to the Operation Status Block shown in the middle of Figure 3–1
on page 3–2.
When the instrument achieves a certain status, the corresponding bit is set to the
OCR. You cannot write to this register. OCR bits that have changed from false
(reset) to true (set) status are set in the OEVR. The function of the OENR is to
mask the OEVR. You can set this mask and take AND with the OEVR to
determine whether or not the OSS bit in the Status Byte Register (SBR) should
be set. Refer to Operation Condition Register (OCR) on page 3–7, Operation
Event Register (OEVR) on page 3–7, and Operation Enable Register (OENR)
on page 3–9, for the contents of these registers.
This block reports on the status of signals and data, such as the accuracy of
entered data and signals generated by the instrument. The register configuration
and process flow are the same as for the Questionable Status Block. Refer to
Questionable Condition Register (QCR) on page 3–7, Questionable Event
Register (QEVR) on page 3–8, and Questionable Enable Register (QENR) on
page 3–9, for the contents of these registers.
Standard/Event Status
Block
Operation Status Block
Questionable Status Block