Tektronix 7623, Инструкция по эксплуатации

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Circuit Description— 7623/R7623 Service
' Pin 14 LO for all other conditions.
Fig. 3-14. Input levels at pin 4 of U324 (source of triggering is
shown in parenthesis).
RIGHT section of S1011 establishes a LO output level at
the emitter of Q314.
Right. In the RIGHT position of the TRIG SOURCE
switch, +5 volts is connected to the emitter of 0314
through S1011 and R312. This produces a HI output level
to the Trigger Channel Switch stage.
Trigger Channel Switch
The Trigger Channel Switch stage determines which
input signal provides the trigger signal to the horizontal
compartment as controlled by the Trigger Mode and ADD
signals from the trigger selection circuitry. Refer to diagram
3 during the following discussion.
Resistors R317 R319 establish the input resistance and
provide a load for the trigger signal from the right vertical
plug-in unit. Resistors R307-R308, located on the Main
Interface circuit, provide the inpt resistance and load for
the left vertical plugin unit. R321 R323-R324 and
R326-R327-R328 establish the operating level of the
Trigger Channel Switch; R321-R323 and R326-R328 set
the current gain for each channel. This stage is made up
primarily of integrated circuit U324. An input/output table
for U324 is shown in Fig. 3-15. U324 provides a high
impedance differential input for the trigger signal from the
left vertical unit at pins 2 and 15, and for the trigger signal
from the right vertical unit at pins 7 and 10. The output
signal at pins 12 and 13 is a differential signal. The sum of
the DC current at pins 12 and 13 is always equal to the sum
of the DC currents at pins 1,8, 9, and 16 in all modes. This
provides a constant DC bias to the stages which follow as
the TRIG SOURCE or the VERT MODE switches are
changed.
When the level at pin 4 is LO (see Trigger Mode and ADD
Signals discussion and Fig. 3-15), the trigger signal
from the left vertical unit passes to the output, while the
trigger signal from the right vertical unit is blocked. A HI
level at pin 4 connects the trigger signal from the right
vertical unit to the output and the trigger signal from the
left vertical unit is blocked. For VERT MODE operation in
the ALT position of the VERT MODE switch, the level at
pin 4 switches between the LO and HI level at a rate
determined by the Vertical Binary stage (see Logic circuit
description). This action obtains the trigger signal from the
left vertical unit when the left vertical unit is being
displayed and from the right vertical unit when it is being
displayed.
When the level at pin 4 is LO and the level at pin 14 is
HI, the trigger signal from both the left and right vertical
units passes to the output pins. This condition occurs only
when the TRIG SOURCE switch is set to VERT MODE and
the VERT MODE switch is set to either ADD or CHOP.
Under this operating mode, the trigger output signal is the
algebraic sum of the trigger input signals from the left and
right vertical units to prevent triggering on the vertical
chopping transition, or only on one signal of an added
display.
Trigger Output Amplifier
The trigger output at pins 12 and 13 of U324 is
connected to the bases of Q344-Q346 to provide the
internal trigger signal for the horizontal unit (via the Main
Interface circuit). The horizontal unit provides a 50-ohm
differential load for this stage. If it is removed from its
compartment, the collector load for O344-Q346 changes
and the voltage at their collectors increases. This stage
prevents this change from affecting the Vertical Signal to
the Output Signal board. CR341 and CR349 clamp the
collectors of Q344 and Q346 at about +0.6 volt to prevent
these transistors from saturating under this no-load con­
dition.
Vertical Signal Buffer
The trigger output signal at pin 12 and 13 of U324 is
also connected to the emitter of a common-base amplifier
Q336 and Q334. The output signal at the collector of Q336
and Q334 is connected to the signals out board.
3-18