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Appendix B: Examples
Option 01 VXI Interface Module User Manual
B–5
WRITE
open:dwell m2,.2; dwell m3,.2; dwell m5,.2;
dwell m6,.2
H
Set the number of times to sequence through the defined scan list to 3.
WRITE
trigger:Sequence:count 3
H
Set the trigger source for the scan list to “immediate”. This programs the
Option 01 to generate an internal trigger after closing a channel in a scan list
and waiting for the close dwell (assigned to the module containing the
channel) to expire.
WRITE
trigger:sequence:source immediate
H
Enable the Operation Complete bit of the Standard Event Status register to
generate a VXI Request True interrupt to the commander of the Option 01
Module.
WRITE
*SRE 32
WRITE
*ESE 1
H
Sequence through the scan list 3 times and set the Operation Complete bit in
the Standard Event Status register when finished.
WRITE
initiate:immediate
WRITE
*OPC
H
After the Option 01 sequences through the scan list three times, it will
generate a VXI Request True interrupt to its commander. When the
commander of the Option 01 detects a Request True interrupt, check the
contents of the Option 01’s Status Byte register.
WRITE
*STB?
READ
096
H
This response indicates that bits 5 and 6 of the Status Byte register are set.
Bit 6 indicates that the Option 01 has generated a request true interrupt. Bit 5
indicates that the Operation Complete bit in the Standard Event Status
register has been set. (This bit was enabled to set bit 5 of the Status Byte
register by the previously issued *ESE 1 command.)
H
Read the Standard Event Status register contents.
WRITE
*ESR?
READ
001
WRITE
*ESR?
READ
000
Note that the second read of the Standard Event Status register is zero
because this register is cleared each time an *ESR? query is received.