MAINBOARD BIOS SETUP
MAINBOARD BIOS SETUP
P5V30-B4 User’s Manual
P5V30-B4 User’s Manual
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EDO DRAMS. This option should be set to
Disabled
if the EDO Read Burst timing is set to
either x333 or x444. *
Disabled
is the default.
Refresh RAS# Assertion
- This option controls the number of clocks RAS# is asserted for
refresh cycles. *
5 CPU Clocks
is the default.
ISA Bus Clock
- This item allows you to select the PCI clock type. PCI CLK/3 or PCI
CLK/4.
Video BIOS Cacheable
- When
Enabled
, the Video BIOS cacheable will cause access to
the video BIOS addressed at C0000H to C7FFFH to be cached. *
Enabled
is the default.
8 Bit I/O Recovery Time
- The recovery time is the length of time, measured in ISA BUS
clocks, that the system will delay after the completion of an input/output request. This delay
takes place because the CPU is operating faster than the input/output bus. Therefore the
CPU must be delayed to allow for the completion of I/O transfers. This item allows you to
determine the recovery time allowed for 8 bit I/O. Choices are from NA, 1 to 8 ISA BUS
clocks. *
NA
is the default.
16 Bit I/O Recovery Time
- This item allows you to determine the recovery time allowed
for 16 bit I/O. Choices are from NA, 1 to 4 ISA BUS clocks. *
NA
is the default.
Memory Hole At 15M-16M
- In order to improve performance, certain space in memory
can be reserved for ISA cards. This memory must be mapped into the memory space below
16 MB. *
Disabled
is the default.
Peer Concurrency
- Peer concurrency means that more than one PCI device can be active
at a time. *
Enabled
is the default.
Passive Release
- The PIIX3 (PCI ISA IDE Xcelerator) provides a programmable Passive
Release mechanism to meet the required master latencies. When
enabled
(default), ISA
masters may see long delays in access to any PCI memory, including the main DRAM array.
Delayed Transaction
- It is used by targets that cannot complete the initial data phase
within the requirements of the PCI 2.1 specification.
Disabled
is the default.
