Tekram Technology P5T30-A4, Руководство пользователя

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MAINBOARD BIOS SETUP MAINBOARD BIOS SETUP
P5T30-A4 User’s Manual P5T30-A4 User’s Manual
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installed. Here, greater delays may be required to preserve the integrity of the data held in
the slower memory chips.
DRAM Timing - DRAM timing is controlled by the DRAM timing registers. The timings
programmed into this register are dependent on the system design. 60ns is the fastest rate.
The 70ns timing is slower and may be required in certain system designs to support loose
layouts or slower memory.
DRAM Leadoff Timing - This Read_Leadoff/Write_Leadoff/RAS#_Precharge timing of
CPU clocks allowed before reads and writes to DRAM are performed. Slower leadoffs may
be required to support slower memories.
DRAM Read Burst (EDO/FP) - Sets the burst mode read timing for two different DRAM
types - (EDO/FP). Burst read and write requests are generated by the CPU in four separate
parts. The first part provides the location within the DRAM where the read or write is to
take place, while the remaining three parts provide the actual data. The lower the timing
numbers, the faster the system will address memory. *
x333/x444 timings is the default.
x222/x333 Read DRAM (EDO/FPM) timings are 2-2-2/3-3-3
x333/x444 Read DRAM (EDO/FPM) timings are 3-3-3/4-4-4
x444/x444 Read DRAM (EDO/FPM) timings are 4-4-4/4-4-4
DRAM Write Burst Timing - Sets the timing for burst mode writes from DRAM. Burst
read and write requests are generated by the CPU in four separate parts. The first part
provides the location within the DRAM where the read or write is to take place, while the
remaining three parts provide the actual data. The lower the timing numbers, the faster the
system will address memory. *
x333 timings is the default.
x222 Write DRAM timings are 2-2-2-2
x333 Write DRAM timings are 3-3-3-3
x444 Write DRAM timings are 4-4-4-4
Fast EDO Lead off - The item allows you to select the Fast EDO Lead Off or not to
enhance the performance.
Refresh RAS# Assertion - This item allows you to select the type of DRAM refresh clock
delay: 4 or 5 Clocks.
SDRAM (CAS Lat/RAS-to-CAS) - This item allows you to select the CAS# latency for all
SDRAM cycles and RAS# to CAS# delay: 2/2 or 3/3.
SDRAM Speculative Read - This item is capable of allowing a DRAM read request to be
generated slightly before the address has been fully decoded. This can reduce all read
latencies. More simply, the CPU will issue a read request and included with this request is
the place (address) in memory where the desired data is to be found. This request is