Te chnologic Sys t e ms
Da t e
Tit le :
Re v:
De s igne r
She e t
of
TS-7680 MX286 CPU
3
LCD
JTAG, I2C
NAND, PWM
MX286 ARM9 CPU
20
Se pt . 1, 2015
B
UARTs , ADC
NC on
MX283
SD Ca rd
SPI Boot
NC on
MX283
NC on
MX283
SD0
SD2
LCD_00 t hru LCD_04
Cont rol Boot Source
All JTAG ha ve 47K int e rna l PU e xce pt RTCK
NC
on MX283
a nd 286
a nd 286
a nd 286
Boot
SPI
RESET#
4 CAN s igna ls
a nd ba ll D7
MX286 a dds
e MMC Int e rfa ce
EN_SPI_BOOT_FLASH is s e t low by CPU
a ft e r done boot ing from SPI
The n SPI s igna ls a re cha nge d t o UART2
SD1
To FPGA
SD3
e MMC
1. 8V
Ha rd s t ra ppe d for SPI
a nd UART3 funct ions
The s e s igna ls a re on t he s a me MX28
pins on bot h Re v. A a nd Re v. B
WIFI_IRQ
PUSH_SW#
FPGA_IRQ
All MODBUS s igna ls
DC_DIO4 t hru DIO6
FPGA_29
LCD_00 t hru D06
B14
ADC0_HS
C14
ADC6
D15
ADC5
D13
ADC4
D9
ADC3
C8
ADC2
C9
ADC1
C15
ADC0
J6
AUART0_CTS/ DEBUG_RXD
J7
AUART0_RTS/ DEBUG_TXD
G5
AUART0_RX
H5
AUART0_TX
K5
AUART1_CTS
J5
AUART1_RTS
L4
AUART1_RX
K4
AUART1_TX
H6
AUART2_CTS
H7
AUART2_RTS
F6
AUART2_RX
F5
AUART2_TX
L6
AUART3_CTS
K6
AUART3_RTS
M5
AUART3_RX
L5
AUART3_TX
U3-A
MX286_CPU_IND
R5
LCD_D23
T5
LCD_D22
U5
LCD_D21
R4
LCD_D20
T4
LCD_D19
U4
LCD_D18
R3
LCD_D17
T3
LCD_D16
U3
LCD_D15
U2
LCD_D14
T2
LCD_D13
T1
LCD_D12
R2
LCD_D11
R1
LCD_D10
P3
LCD_D09
P2
LCD_D08
P1
LCD_D07
N2
LCD_D06
M3
LCD_D05
M2
LCD_D04
L3
LCD_D03
L2
LCD_D02
K3
LCD_D01
K2
LCD_D00
P5
LCD_CS/ ENABLE
N1
LCD_DOTCLK
N5
LCD_ENABLE
M1
LCD_HSYNC
P4
LCD_RD_E/ VSYNCH
M6
LCD_RESET/ VSYNCH
M4
LCD_RS/ DOTCLK
L1
LCD_VSYNC
K1
LCD_WR_RWN/ HSYNCH
U3-D
MX286_CPU_IND
Boot
SPI
F7
SAIF0_BITCLK/ UART4_RXD/ PWM5
G6
SAIF0_LRCLK/ PWM4
G7
SAIF0_MCLK/ PWM3
E7
SAIF0_SDATA0/ UART4_TXD/ PWM6
E8
SAIF1_SDATA0/ PWM7
D7
SPDIF
A4
SSP0_CMD
B4
SSP0_DATA7/ SSP2_SCK
D5
SSP0_DATA6/ SSP2_CMD
C5
SSP0_DATA5/ SSP2_D3
B5
SSP0_DATA4/ SSP2_D0
A5
SSP0_DATA3
D6
SSP0_DATA2
C6
SSP0_DATA1
B6
SSP0_DATA0
D10
SSP0_DETECT
A6
SSP0_SCK
C1
SSP1_CMD
E1
SSP1_DATA3
D1
SSP1_DATA0
B1
SSP1_SCK
B3
SSP2_MISO/ UART3_RXD
C3
SSP2_MOSI/ UART2_TXD
A3
SSP2_SCK/ UART2_RXD
D4
SSP2_SS2/ SSP2_D2
D3
SSP2_SS1/ SSP2_D1
C4
SSP2_SS0/ UART3_TXD
B2
SSP3_MISO
C2
SSP3_MOSI
A2
SSP3_SCK
D2
SSP3_SS0
U3-F
MX286_CPU_IND
1
8
RN21-A
10K
3
6
RN18-C
47K
U7
GPMI_D03/ SSP1_D3
R8
GPMI_D02/ SSP1_D2
T8
GPMI_D01/ SSP1_D1
U8
GPMI_D00/ SSP1_D0
R6
SSP3_SCK
L8
CAN_RX0
M8
CAN_TX0
N8
GPMI_RDY1/ SSP1_CMD
N6
GPMI_RDY0/ USB0_ID
L9
SSP3_MOSI
P8
GPMI_WRN/ SSP1_SCK
C7
I2C0_SCL
D8
I2C0_SDA
E14
JTAG_RTCK
E11
JTAG_TCK
E12
JTAG_TDI
E13
JTAG_TDO
D12
JTAG_TMS
D14
JTAG_TRST
T6
GPMI_D07
U6
GPMI_D06
R7
GPMI_D05
T7
GPMI_D04
P6
SSP3_CS1#
N7
SSP3_MISO
N9
SSP3_CS0#
M7
CAN_TX1
M9
CAN_RX1
P7
SSP3_CS2#
E10
PWM4
E9
PWM3
K8
PWM2/ USB0_ID
L7
PWM1/ DEBUG_TXD
K7
PWM0/ DEBUG_RXD
U3-C
MX286_CPU_IND
4
5
RN19-D
47K
6
3
RN20-C
10K
