TS-7400/TS-9441 MANUAL
HARDWARE COMPONENTS
the WDT counter begins. The application software can reset this counter at any time by
“feeding” the WDT. If the WDT counter reaches the timeout period, then a full system
reset occurs.
Table: Watchdog Timeout Register
Value
MSB
MID
LSB
Timeout Period
0x00
0
0
0
Watchdog Disabled
0x01
0
0
1
250 mS
0x02
0
1
0
500 mS
0x03
0
1
1
1 second
0x04
1
0
0
-- Reserved
0x05
1
0
1
2 seconds
0x06
1
1
0
4 seconds
0x07
1
1
1
8 seconds
In order to load the WDT Control register, the WDT must first be “fed”, and then within 30
uS, the WDT control register must be written. Writes to this register without first doing a
“WDT feed”, have no affect. In order to clear the WDT counter (feeding the watchdog), a
value of Hex 05 must be written to the WDT Feed register.
By default, a user process does not have the physical address space (access) of the
watchdog registers mapped. When using the Linux OS, the watchdog can be reached
from user C code by using the mmap() system call on the /dev/mem special file to map
the areas of physical address space into process user address space. See section 3.4.
!
Warning
Use only the Watchdog Timer implemented by Technologic Systems in the CPLD.
The Watchdog Timer included in the EP9302 has serious problems.
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