LPC1224_BO_SRM
Board v0.3
Note
: Refer to the LPC1224 documentation from NXP for full list and documentation of the LPC1224
features. Here are only the descriptions of the features used on the module.
4.1.1 Internal RAM
The LPC1224FBD48/101 has 4kB of internal SRAM mapped in one block at address 0x1000 0000.
4.1.2 Internal Flash
The LPC1224FBD48/101 has 32kB of internal FLASH memory, mapped at address 0x0000 0000. The flash me-
mory programming requires no additional hardware thanks to the In-System Programming (ISP) and In-Application
Programming (IAP) on-chip bootloader software.
See section
4.1.6
(Reset and ISP mode) or sections
5.2
(Code Compilation) and
5.3
(Uploading binary on target)
for more information on internal FLASH memory.
4.1.3 Communication interfaces
The module makes use of the following communication interfaces found on the LPC1224 :
•
Two UARTs
: UART0 and UART1 are connected to P1 header and to the USB to UART bridge through
J3 and J4 jumpers.
UART0 is used for In-System Programming of the LPC1224.
•
One I2C bus interface
supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1
Mbit/s. I2C is connected to P1 header. See section
4.2
for more information.
•
One SSP/SPI controller
with FIFO and multi-protocol capabilities. The SPI bus is also connected to P1
header.
4.1.4 GPIO
The module gives access to 34 GPIO pins dispatched on P1 and P2 connectors.
Refer to tables
2
and
3
for details of the signals available on these GPIO and to the LPC1224 documentation
from NXP for full list of features for each GPIO.
4.1.5 ADC
The last six GPIO pins on P2 connector are inputs channels 0 to 5 for the 10-bit ADC of the LPC1224 micro-
controller.
The internal ADC uses the voltage on the Vref pin as reference voltage for the conversion. The LPC1224 break-out
board integrates a 3.0V reference voltage LDO to provide a stable and accurate Vref to the LPC1224.
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