From POWER
TRANSFORMER
1
8
W501
2
3
4
5
6
7
9
12
13
14
15
16
17
18
A.GND
+B(10V)
SUR L
SUR R
19
11
10
CT.GND
SH FL1
DATA
D.GND
TUNER L/C
TUNER Rch
Lch IN
Rch IN
S.W
MIC
-B(-10V)
V.GND
CS/REQ
CLK
SH FL2
20
SYNC
+B5
Rch
Rch
-B3
To SOUND PROCESSOR
BLOCK DIAGRAM
LC72
CE
LC72
DI/ST
LC72
CK
D
ATA
1
CLK1
D
ATA
IN
CE1
3
4
5
LC72
DO
2
C2BBFD000404
IC901
SYSTEM CONTROL / FL DRIVE
Rch
94
SH
CS
97
SH
CK
95
96
SH
DO
SH
DI
SHSYNC
100
SD
21
SH
REQ
SW CONT.
12
X0
X1
14
A
B
C
11
10
9
G
8
2
13
BU4053BCFE2
SIGNAL SELECTOR
1
15
Y1
Y0
V
DD
16
+B4
V
SS
7
-B3
6
ST/A
V
.
6CH
SD
SA-DV290(EE,GN) BLOCK DIAGRAM
+B8
Q401
TA2011S
MIC2
MIC1
VR401
(MIC VOL)
+B4
MIC
AMP
MIC
AMP
25
MIC DET
AM ANT
FM ANT
Z101 TUNER PACK
RAN0005EM-2:EE
ENG06502Q:GN
8
(6)
3
7
9
11
10
DO
CL
DI
CE
SD
Lch
(Rch)
D
ATA
1
CLK1
D
ATA
IN
CE1
SD
C1BB00000527
RDS SIGNAL DEMODULATOR
CLOCK
RECOVERY
(1187.5kHz)
RDDR
RDCL
IDR
RDS-ID
DETECT/
RAM
57kHz
BPF
(SCF)
PLL
(57kHz)
VREF
CIN
FLOUT
VREF
VDDA/D
VssA/D
MPX IN
TEST
XOUT
XIN
OSC/DIVIDER
CLK(4.332MHz)
8
9
7
2
4,10
3,11
+B2
1
5
6
14
15
16
X151
(4.332MHz)
REFERENCE
VOLTAGE
TEST
ANTIALIASING
FILTER
SMOOTHING
FILTER
DATA
DECODER
MODE
12
13
RST
4
+B2
1
2
+B1
GND
+15V
+7V
DET
5
RDS
DA
T
A
RDDR
RDS
CLK
RDCL
28
27
RDDR
RDCL
For [EE] area.
FL1
FL2
For [GN] area.
For [GN] area.
Содержание SA-DV290EE
Страница 9: ...Follow the Step 1 Step 3 of item 5 1 9...
Страница 10: ...Check the main P C B as shown below 5 4 Replacement for the regulator transistor 10...
Страница 24: ...24...
Страница 27: ...27...
Страница 33: ...15 2 SA DV290GN 33...
Страница 34: ...16 Packaging 34...
Страница 35: ...17 Schematic Diagram for printing with A4 size K0305 YH HM 35...
Страница 48: ......