TAM-3517 HARDWARE MANUAL rev B
July 3 2012, TechNexion
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5.4
NAND Flash
5.4.1
Micron MT29F4G16ABBDAHC
NAND on the TAM-3517 is populated as Micron MT29F4G16ABBDAHC and connected 16 bit
wide to the AM3517 GPMC bus.
The default TAM-3517 supports the chip which provides 512MB of addressable space.
The GPMC_nCS0 signal is used for its selection.
Features:
• Open NAND Flash Interface (ONFI) 1.0-compliant
• Single-level cell (SLC) technology
• Organization
Page size x8: 2112 bytes (2048 + 64 bytes)
Page size x16: 1056 words (1024 + 32 words)
Block size: 64 pages (128K + 4K bytes)
Plane size: 2 planes x 2048 blocks per plane
Device size: 4Gb: 4096 blocks;
• Array performance
Read page: 25μs 3
Program page: 20
0μs (TYP: 1.8V, 3.3V)3
Erase block: 700μs (TYP)
• Command set: ONFI NAND Flash Protocol
• Advanced command set
Program page cache mode4
Read page cache mode 4
One-time programmable (OTP) mode
Two-plane commands 4
Interleaved die (LUN) operations
Read unique ID
Block lock (1.8V only)
Internal data move
• Operation status byte provides software method for
detecting
Operation completion
Pass/fail condition
Write-protect status
• Ready/Busy# (R/B#) signal provides a hardware
method of detecting operation completion
• WP# signal: Write protect entire device
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