Teac DV-H500, Руководство по обслуживанию

Страница: 16 / 58

2-16
Pin Name Type Function
EXTERNAL MEMORY INTERFACE
161-170, 173-183 ADR[1:21] I/O External Memory Address Bus
141-148, 151-158 DATA[0:15] I/O External Memory Data Bus
128
RAS1/HOLDREQ
O DRAM RAS or reserved
136 WAIT/READY I/O External Wait States or Reserved
133
R/W/DMAACK
I/O DRAM R/W Strobe or Reserved
121, 122 BE[0:1] O Byte enable
129
CAS0/HOLDACK
O/I DRAM CAS or Reserved
132
CAS1/DMAREQ
O DRAM CAS or Reserved
124-126
CE[1:3]
O Chip Select for Banks 1 - 3
135
CS
I Reserved
137 PROCCLK I/O ST20 Clock or Reserved
127
RAS0/CE0
O DRAM RAS or Chip Select for Bank 0
134 DMAXFER I Reserved
138
PPC_MODE
I Reserved
123
OE
I/O Output Enable or Reserved
SDAV/P1394 INTERFACE
30 TEST1 I/O DATA_RX/STROBE_TX (SDAV Mode) or SDAV_CLK
(P1394 Mode) or PARA_DATA[6] (DVD//)
31 TEST2 I/O ST R O BE _ R X/ D AT A _ TX ( SD A V M od e) o r
D A T A _ I N / D A T A _ O UT ( P 13 9 4 M od e ) o r
PARA_DATA[7] (DVD//)
32 TEST3 I/O Direction (SDAV Mode) or DATA_VALID In/Out (P1394
Mode)
MISCELLANEOUS
41 TEST5 O NRSS_OUT (DVB/DSS)
33 TEST4 I PARA_DVALID (DVD//) : Data valid on front end parallel
interface
PERIPHERALS
FRONT-END
INTERFACE
DMA
GENERIC
EMI
SDRAM I/F
DENC
CENTRAL
COMMAND
PORT
DMAs
COMMUNICATIONS
ARBITER
ST20 ARBITER & MEMORY CONTROLLER
CPU
(C2)
CLOCK
GENERATION
SMI
SDRAM
BLOCK MOVE
CD FIFOs COMMAND I/F
SDRAM ARBITER (LMC)
OSD AND
SP DECODER
VIDEO
DECODER
AUDIO
DECODER
CACHE SUBSYSTEM
RID TAP
REFILL
CONTROL
ICACHE
SRAM
DCACHE
DIAGNOSTIC
CONTROLLER
CPU ARBITER
MPEG MPEG
TELETEXT
DEBUG
BLOCK MOVE
P
A
D
S
P
A
D
S
SDAV/P1394
INTERFACE
DMA
BLOCK DIAGRAM