Teac CT-W2850S1, Руководство по обслуживанию

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Pin4=Current Sense Input
Pin5=Synchronization Input
Pin6=GND
Pin7=Gate Drive
Pin8=Vcc
16.15.
STV9379:
16.15.1.
DESCRIPTION
Designed for monitors and high performance TVs, the STV9379FA vertical deflection booster can
handle flyback voltage up to 90V. Further to this, it is possible to have a flyback voltage, which is more
than the double of the supply (Pin 2). This allows to decrease the power consumption, or to decrease
the flyback time for a given supply voltage.
The STV9379FA operates with supplies up to 42V and provides up to 2.6A
PP
output current to drive
the yoke.
The STV9379FA is offered in HEPTAWATT package.
16.15.2.
PINNING
Pin1 : Output Stage Supply
Pin2 : Output
Pin3 : GND or Negative Supply
Pin4 :
Flyback Supply
Pin5 :
Supply Voltage
Pin6 :
Inverting Input
Pin7 : Non-inverting Input
16.16.
MSP34XX :
MSP3410D
The MSP3410D is an I2C controlled single-chip multistandard sound processor for applications in analog and
digital TV sets. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog
AF-out is performed in a single-chip covering all European TV-standards. It is designed to simultaneously perform
digital demodulation and decoding of NICAM-coded TV stereo sound, as well as demodulation of FM-mono TV
sound and two FM systems according to the German or Korean terrestrial specs. It is also possible to do AM-
demodulation according to the SECAM system. There is AGC for analog inputs: 0.14 - 3Vpp. All demodulation
and filtering is performed on chip and is individually programmable. All digital NICAM standards (B/G, L, and I)
are realised. Only one crystal clock (18.432Mhz) is necessary. External capacitors at each crystal pin to ground are
required. They are necessary for tuning the open-loop frequency of the internal PLL and for stabilising the
frequency in closed-loop operation. The higher the capacitors, the lower the clock frequency result. The nominal
free running frequency should match the centre of the tolerance range between 18.433 and 18.431Mhz as closely
as possible. By means of standardised I2S interface, additional feature processors (DPL35xx, Dolby Prologic
processor for this chassis) can be connected to the IC.
I2S bus interface consists of five pins:
I2S_DA_IN1… 2
for input four channels (two channels per line) per sampling cycle (32Khz).
I2DA_OUT, for output, two channels per sampling cycle (32KHz).
I2S_CL, for timing of the transmission of I2S serial data, 1.024Mhz.
I2S_WS, for the word strobe line defining the left and right sample.
Features:
n
5-band graphic equalizer (as in MSP3400C)
n
Enhanced spatial affect (pseudo stereo / base-width enlargement as in MSP3400C)
n
Headphone channel with balance, bass treble, loudness
n
Balance for loudspeaker and headphone channels in dB units (optional)