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23

22” TFT TV Service Manual

13/10/2004

NC (Pin 3)

No connection.

V

DD

(Pin 4)

This is the +5V power pin for the chip.

HSYNC (Pin 5)

This pin inputs a horizontal synchronize signal. It is negative polarity by default. The leading edge of
HSYNC synchronizes its internal horizontal timing. The maximum input ratio between PIXin/HSYNC should
not greater than 1580 for displaying 12X18 font matrix. For displaying 10X18 font matrix, this ratio should
not greater than 1280.

RESET (Pin 6)

An active low signal will reset ROW15 and ROW16 control registers. Refer to Control Registers section for
default set-tings. A proper RC network have to be tighten to this pin to ensure the device initialize properly
during power up. Refer to the application diagram.

SDA (Pin 7)

Data and control message are being transmitted to this chip from a host MCU via M_bus systems. This
wire is configurated as a uni-directional data line. (Detailed description of protocols will be discussed in the
M_BUS section).

SCL (Pin 8)

A separate synchronizing clock input from the transmitter is required for M_Bus protocol. Data is read at
the rising edge of each clock signal.

V

DD

(Pin 9)

This is the power pin for the digital logic of the chip.

VSYNC (Pin 10)

Similar to Pin 5, this pin inputs a vertical synchronize signal to synchronize the vertical control circuit. It is
negative polarity by default.

V

DD

(I) (Pin 11)

This is the voltage supply of RGB outputs when low intensity of Windows/ROW is selected. The RBG
output level would be equal to VDD(I) in this case. Please refer to Row Attribute/Window registers for more
detail. The input voltage for this pin should be equal to or less than V DD (Pin 17) for normal operation.

FBKG (Pin 12)

This pin will output a logic high while displaying characters or windows. It is defaulted to high impedance
state after power on, or when there is no output. An external 10

κΩ

resistor pulled low is recommended to

avoid level toggling caused by hand effect when there is no output.

B,G,R (Pin 13, 14, 15)

LMOSD2-16 color outputs in CMOS level to the host monitor. These three signals are open drain outputs if
3_STATE bit is set and the color intensity is inactive. Otherwise, they are active high push-pull outputs.
See “REGISTERS” for more information. These pins are in high impedance state after power on.

V

SS

(Pin 24)

This is the ground pin for the digital logic of the chip.

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Содержание 17MB10

Страница 1: ...TEAC 22 TFT IDTV SERVICE MANUAL ...

Страница 2: ... 2 Features 4 11 1 3 Applications 4 11 1 4 Connection Diagrams 4 11 2 LM2576 5 11 2 1 General Description 5 11 2 2 Features 5 11 2 3 Pin description 5 11 3 LM317T 6 11 3 1 Description 6 11 3 2 Features 6 11 4 TFMS5360 6 11 4 1 Description 6 11 4 2 Features 6 11 5 ST24LC21 7 11 5 1 Description 7 11 5 2 Features 7 11 5 3 Pin connections 7 11 6 SST37VF040 8 11 6 1 Description 8 11 6 2 Features 8 11 6...

Страница 3: ...ription 22 11 18 2 Features 22 11 18 3 Pin Description 22 11 19 MC34063 24 11 19 1 Description 24 11 19 2 Features 24 11 19 3 Pin connections 24 11 20 MSP34X0G 25 11 20 1 Introduction 25 11 20 2 Features 25 11 20 3 Pin connections 26 11 21 DS90C385 28 11 21 1 General Description 28 11 21 2 Features 28 11 21 3 Pin Descriptions 28 11 22 4053B 31 11 22 1 General Description 31 11 22 2 Pin Description...

Страница 4: ...7 2 Features 40 12 7 3 Pin Description 40 12 8 24C32 41 12 8 1 General Description 41 12 8 2 Features 41 12 8 3 Pin Description 41 12 9 STV0360 42 12 9 1 General Description 42 12 9 2 Features 42 12 9 3 Pin Description 42 12 10 MAX809 45 12 10 1 General Description 45 12 10 2 Features 45 12 10 3 Pin Description 45 12 11 TDCC2345TV39A 46 12 11 1 General Description 46 12 11 2 Pin Description 46 13 ...

Страница 5: ...led PLL tuning via I2 C bus 4 Off air channels S cable channels and Hyper band 5 Compact size 6 Complies to CENELEC EN55020 and EN55013 Pinning 1 Gain control voltage AGC 4 0V Max 4 5V 2 Tuning voltage 3 I C bus address select Max 5 5V 4 I C bus serial clock Min 0 3V Max 5 5V 5 I C bus serial data Min 0 3V Max 5 5V 6 Not connected 7 PLL supply voltage 5 0V Min 4 75V Max 5 5V 8 ADC input 9 Tuner su...

Страница 6: ...ers Normal Mode 33 33 MHz CPU clock Power Save mode 8 33 MHz 7 3 Microcontroller Features 8bit 8051 instruction set compatible CPU 33 33 MHz internal clock max 0 360 µs min instruction cycle Two 16 bit timers Watchdog timer Capture compare timer for infrared remote control decoding Pulse width modulation unit 2 channels 14 bit 6 channels 8 bit ADC 4 channels 8 bit UART rxd txd 7 4 Memory Up to 128...

Страница 7: ...ital or analogue inputs for the ADC Port2 One 2 bit I O port with secondary function P4 2 4 3 4 7 One 4 bit I O port with secondary function P4 0 4 1 4 4 Not available in P SDIP 52 8 SERIAL ACCESS CMOS 16K 2048 8 EEPROM ST24C16 The ST24C16 is a 16Kbit electrically erasable programmable memory EEPROM organised as 8 blocks of 256 8 bits The memory is compatible with the I C standard two wire serial ...

Страница 8: ...fixed voltages 1 8V 2 5V 2 85V 3 3V and 5V The LM1117 offers current limiting and thermal shutdown Its circuit includes a zener trimmed bandgap reference to as sure output voltage accuracy to within 1 The LM1117 series is available in SOT 223 TO 220 and TO 252 D PAK packages A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability 11 1 2 Featur...

Страница 9: ...nk is required or its size could be reduced dramatically A standard series of inductors optimized for use with the LM2576 are available from several different manufacturers This feature greatly simplifies the design of switch mode power supplies The LM2576 features include a guaranteed 4 tolerance on output voltage within specified input voltages and output load conditions and 10 on the oscillator...

Страница 10: ...o be used to make a programmable output regulator or by connecting a fixed resistor between the adjustment and output the LM317 can be used as a precision current regulator 11 3 2 Features Output Current in Excess of 1 5 A Output Adjustable between 1 2 V and 37 V Internal Thermal Overload Protection Internal Short Circuit Current Limiting Constant with Temperature Output Transistor Safe Area Compe...

Страница 11: ...ly mode except when the power supply is removed The device operates with a power supply value as low as 2 5V Both Plastic Dual in Line and Plastic Small Outline packages are available 11 5 2 Features 1 million Erase Write cycles 40 years data retention 2 5V to 5 5V single supply voltage 400k Hz compatibility over the full range of supply voltage Two wire serial interface I2 C bus compatible Page W...

Страница 12: ... currently use UV EPROMs OTPs and mask ROMs 11 6 2 Features Organized as 64K x8 128K x8 256K x8 512K x8 2 7 3 6V Read Operation Superior Reliability Endurance At least 1000 Cycles Greater than 100 years Data Retention Low Power Consumption Active Current 10 mA typical Standby Current 2 µA typical Fast Read Access Time 70 ns 90 ns Latched Address and Data Fast Byte Program Operation Byte Program Ti...

Страница 13: ...e same reference voltage on each input in order to have no differential voltage when switching two RGB generators An AC output signal higher than 2 Vpp makes gain going slowly down to 0dBto protect the TV set video amplifier from saturation Fast blanking output is a logical OR between FB1 Pin 8 and FB2 Pin 10 11 7 2 Features 25MHz Bandwidth Crosstalk 55dB Short circuit to ground or VCC protected A...

Страница 14: ...n In other case 1 word of 16 bits is necessary to determine one configuration 11 8 2 13 5 2 Features 20MHz Bandwidth Cascadable with another TEA6415C Internal address can be changed by pin 7 voltage 8 Inputs CVBS RGB MAC CHROMA 6 Outputs Possibility of MAC or chroma signal for each input by switching off the clamp with an external resistor bridge Bus controlled 6 5dB gain between any input and out...

Страница 15: ... 80 pin PQFP package 11 9 2 Pin Connections and Short Descriptions NC not connected LV if not used leave vacant X obligatory connect as described in circuit diagram SUPPLYA 4 75 5 25 V SUPPLYD 3 15 3 45 V Pin No PQFP 80 pin Pin Name Type Connection if not used Short Description 1 B1 CB1IN IN VREF Blue1 Cb1 Analog Component Input 2 G1 Y1IN IN VREF Green1 Y1 Analog Component Input 3 R1 CR1IN IN VREF...

Страница 16: ... Front Sync Horizontal Clamp Pulse Front End Horizontal Sync Output 56 MSY HS IN OUT LV Main Sync Horizontal Sync Pulse 57 VS OUT LV Vertical Sync Pulse 58 FPDAT VSYA IN OUT LV Front End Back End Data Front End Vertical Sync Output 59 VSTBYY SUPPLYA X Standby Supply Voltage 60 CLK5 OUT LV CCU 5 MHz Clock Output 61 NC LV or GNDD Not Connected 62 XTAL1 IN X Analog Crystal Input 63 XTAL2 OUT X Analog...

Страница 17: ...abilities based on parallel attributes and Pixel oriented characters DRCS The 8 bit Microcontroller runs at 360 ns cycle time min Controller with dedicated hardware does most of the internal TTX acquisition processing transfers data to from external memory interface and receives transmits data via I2 C firmware user interface The slicer combined with dedicated hardware stores TTX data in a VBI buf...

Страница 18: ...Frequency Control AFC detector with 4 bit digital to analog converter AFC bits via I2 C bus readable TakeOver Point TOP adjustable via I2 C bus or alternatively with potentiometer Fully integrated sound carrier trap for 4 5 5 5 6 0 and 6 5 MHz controlled by FM PLL oscillator Sound IF SIF input for single reference Quasi Split Sound QSS mode PLL controlled SIF AGC for gain controlled SIF amplifier ...

Страница 19: ...N DESCRIPTION PIN VALUE OUTA 1 Output A Voltage swing Min 0 75V Max 4 25V INA neg 2 Inverting input A Vo clip Min 1400mVrms INA pos 3 Non inverting input A 2 5V VSS 4 Negative supply 0V INB pos 5 Non inverting input B 2 5V INB neg 6 Inverting input B Vo clip Min 1400mVrms OUTB 7 Output B Voltage swing Min 0 75V Max 4 25V VDD 8 Positive supply 5V Min 3 0V Max 7 0V 11 13 AN7522N 11 13 1 General desc...

Страница 20: ...greater than most analog switches offered today A single 5V supply is all that is required for operation The PI5V330 offers a high performance low cost solution to switch between video sources The application section describes the PI5V330 replacing the HC4053 multiplier and buffer amplifier 11 14 2 Features High performance low cost solution to switch between video sources Wide bandwidth 200 MHz L...

Страница 21: ...The design kit is complete with hardware and software Software includes G Probe debug software G Wizard register calculator and G TV application source code The 6015RD1 is a related reference board that outputs analog YpbPr RGB 11 15 2 Features Dual channel gm6015 based LCD TV system Industry leading Crystal Cinema Plus video scan conversion Inputs i Component analog YPbPr RGB ii 480 576I 480 576P...

Страница 22: ...ed in the section Keyboard operation 11 16 2 Features Low voltage requirement Biphase transmission technique Single pin oscillator Test mode facility 11 16 3 Pinning Pin Mnemonic Function 1 X7 IPU Sense input from key matrix 2 SSM I Sense mode selection input 3 Z0 Z3 IPU Sense inputs from key matrix 7 MDATA OP3 Generated output data modulated with 1 12 the oscillator frequency at a 25 duty factor ...

Страница 23: ...vided in a space saving 80 lead LQFP surface mount plastic package and is specified over the 0C to 70C temperature range 11 17 2 Features 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0 5 V to 1 0 V Analog Input Range 500 ps p p PLL Clock Jitter at 110 MSPS 3 3 V Power Supply Full Sync Processing Sync Detect for Plugging Midscale Clamping Power Down Mode Low Power 500 mW Typical 4 2 2 ...

Страница 24: ...ctive The input includes a Schmitt trigger for noise immunity with a nominal input threshold of 1 5 V VSYNC Vertical Sync Input This is the input for vertical sync SOGIN Sync on Green Input This input is provided to assist with processing signals with embedded sync typically on the GREEN channel The pin is connected to a high speed comparator with an internally generated threshold The threshold le...

Страница 25: ...oper operation the pixel clock generator PLL requires an external filter Connect the filter shown in Figure 6 to this pin For optimal performance minimize noise and parasitics on this node POWER SUPPLY VD Main Power Supply These pins supply power to the main elements of the circuit They should be as quiet and filtered as possible VDD Digital Output Power Supply A large number of output pins up to ...

Страница 26: ...ght of character and row to row spacing and full screen erasing and Fade In Fade Out are also incorporated There are 8 color selections for any individual character display with row intensity attribute and window intensity attribute to expand the color mixture on OSD menu 11 18 2 Features Totally 512 Fonts Including 496 Standard Fonts and 16 Multi Color Fonts 10x18 or 12x18 Font Matrix Selection M...

Страница 27: ...Data is read at the rising edge of each clock signal VDD Pin 9 This is the power pin for the digital logic of the chip VSYNC Pin 10 Similar to Pin 5 this pin inputs a vertical synchronize signal to synchronize the vertical control circuit It is negative polarity by default VDD I Pin 11 This is the voltage supply of RGB outputs when low intensity of Windows ROW is selected The RBG output level woul...

Страница 28: ...d duty cycle oscillator with an active current limit circuit driver and high current output switch This series was specifically designed to be incorporated in Step Down and Step Up and Voltage Inverting applications with a minimum number of external components 11 19 2 Features Operation from 3 0 V to 40 V Input Low Standby Current Current Limiting Output Switch Current to 1 5 A Output Voltage Adju...

Страница 29: ... MSP 34x0D The MSP 34x0G further simplifies controlling software Standard selection requires a single I C transmission only The MSP 34x0G has built in automatic functions The IC is able to detect the actual sound standard automatically Automatic Standard Detection Furthermore pilot levels and identification signals can be evaluated internally with subsequent switching between mono stereo bilingual...

Страница 30: ... C data 9 9 7 2 1 I2C_CL IN OUT OBL I 2 C clock 10 8 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN OBL Stand by low active 12 6 5 79 62 ADR_SEL IN OBL I 2 C bus address select 13 5 4 78 61 D_CTR_I O_0 IN OUT LV D_CTR_I O_0 14 4 3 77 60 D_CTR_I O_1 IN OUT LV D_CTR_I O_1 15 3 76 59 NC LV Not connected 16 2 75 58 NC LV Not connected 17 NC LV Not connected 18 1 2 74 57 AUD_CL_OUT OUT LV Audio cloc...

Страница 31: ...4 28 34 26 SC2_OUT_L OUT LV SCART output 2 left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2 right 52 32 NC LV Not connected 53 32 31 24 NC LV Not connected 54 31 26 30 23 DACM_SUB OUT LV Subwoofer output 55 30 29 22 NC LV Not connected 56 29 25 28 21 DACM_L OUT LV Loudspeaker out left 57 28 24 27 20 DACM_R OUT LV Loudspeaker out right 58 27 23 26 19 VREF2 OBL Reference ground 2 59 26 22 25 18 D...

Страница 32: ...TxINPUTs Tx power consumption 130 mW typ 85MHz Grayscale Tx Power down mode 200µW max Supports VGA SVGA XGA and Dual Pixel SXGA Narrow bus reduces cable size and cost Up to 2 38 Gbps throughput Up to 297 5 Megabytes sec bandwidth 345 mV typ swing LVDS devices for low EMI PLL requires no external components Compatible with TIA EIA 644 LVDS standard Low profile 56 lead or 48 lead TSSOP package DS90C...

Страница 33: ... P G1 GND G A5 LVDS VCC P G6 GND G A6 TxCLKOUT O B3 LVDS GND G A7 TxCLKOUT O B4 LVDS GND G A8 TxOUT3 O B7 LVDS GND G B1 TxIN1 I D5 LVDS GND G B2 TxIN0 I C6 PLL GND G B3 LVDS GND G D6 PLL GND G B4 LVDS GND G D7 PWR DOWN I B5 TxOUT2 O G5 R_FB I B6 TxOUT3 O C8 TxCLKIN I B7 LVDS GND G B2 TxIN0 I B8 NC B1 TxIN1 I C1 TxIN3 I D2 TxIN2 I C2 NC C1 TxIN3 I C3 NC D1 TxIN4 I C4 TxOUT1 O F1 TxIN5 I C5 TxOUT2 O...

Страница 34: ... Blue and 3 control lines FPLINE FPFRAME and DRDY also referred to as HSYNC VSYNC Data Enable TxOUT O 3 Positive LVDS differentiaI data output TxOUT O 3 Negative LVDS differential data output TxCLKIN I 1 TTL Ievel clock input Pin name TxCLK IN R_FB I 1 Programmable strobe select TxCLK OUT O 1 Positive LVDS differential clock output TxCLK OUT O 1 Negative LVDS differential clock output PWR DOWN I 1...

Страница 35: ...lly controlled analog switches having low ON impedance and very low OFF leakage current These multiplexer circuits dissipate extremely low quiescent power over the full VDD VSS and VDD VEE supply voltage ranges independent of the logic state of the control signals When a logic 1 is present at the inhibit input terminal all channel are off The HCC HCF4053B is a triple 2 channel multiplexer having t...

Страница 36: ...OM technology and provides a low power and low voltage operation The IS24CXX family features a write protection feature and is available in 8 pin DIP and 8 pin SOIC packages 11 23 2 Features Low Power CMOS Technology Low Voltage Operation 100 KHz 1 8V and 400 KHz 5V Compatibility Hardware Data Protection Sequential Read Feature Filtered Inputs for Noise Suppression 8 pin PDIP and 8 pin SOIC packag...

Страница 37: ...s with no regard to the supply voltage This device can be used to interface 5V to 3V All inputs and outputs are equipped with protection circuits against static discharge 11 24 2 Features 5V tolerant inputs High speed tPD 5ns MAX at VCC 3V Low power dissipation ICC 1µA MAX at TA 25 C Power down protection on inputs and outputs Symmetrical output impedance IOH IOL 24mA MIN at VCC 3V Balanced propag...

Страница 38: ...xtremely efficient and reliable device for use in a wide variety of applications The SO 8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple die capability making it ideal in a variety of power applications With these improvements multiple devices can be used in an application with dramatically reduced board space The package is designed for vapor ph...

Страница 39: ...s ideal for set top boxes featuring trick modes such as live TV recording pausing and time shifting The STi5518 is backward compatible with the popular STi5500 set top box decoder allowing easy migration from the previous generation The high level of integration in a single PQFP 208 package makes the STi5518 ideally suited for low cost high volume set top box applications 12 2 MAX232_SMD 12 2 1 Ge...

Страница 40: ...cated in silicon gate C2 MOS technology It has the same high speed performance of LSTTL combined with true CMOS low power consumption As the internal circuit is composed of a single stage inverter it can be used in crystal oscillator All inputs are equipped with circuits against static discharge and transient excess voltage 12 3 2 Pin Description ...

Страница 41: ...er only in the supported interface format The CS4334 family is based on delta sigma modulation where the modulator output controls the reference voltage input to an ultra linear analogue low pass filter This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency The CS4334 family contains on chip digital de emphasis operat...

Страница 42: ... clock cycle Range of operating frequencies programmable latencies allows the same device to be useful for a variety of high bandwidth high performance memory system applications 12 6 2 Features JEDEC standard 3 3V power supply LVTTL compatible with multiplexed address Four banks Pulse RAS MRS cycle with address key programs All inputs are sampled at the positive going edge of the system clock Clo...

Страница 43: ...39 22 TFT TV Service Manual 13 10 2004 ...

Страница 44: ...OM compatibility MXIC Flash technology reliably stores memory contents even after 100 000 erase and program cycles The MXIC cell is designed to optimize the erase and programming mechanisms In addition the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling The MX29LV160T B MX29LV160AT AB uses a 2 7V 3 6V VCC s...

Страница 45: ...ware Data Protection 32 Byte Page Write Mode Partial Page Writes Allowed Self Timed Write Cycle 10 ms max High Reliability Automotive Grade and Extended Temperature Devices Available 8 Pin JEDEC PDIP 8 Pin JEDEC SOIC 8 Pin EIAJ SOIC and 8 pin TSSOP Packages 12 8 3 Pin Description SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data...

Страница 46: ...ation eliminates the need for external components when using wide band AGC tuners In addition to all the demodulation and FEC forward error correction functions required for recovery of the QAM modulated bit streams with very low BER it also includes several features that give easy and immediate access to various quality monitoring parameters or lock status The STV0360 also provides output such as...

Страница 47: ...43 22 TFT TV Service Manual 13 10 2004 ...

Страница 48: ...44 22 TFT TV Service Manual 13 10 2004 ...

Страница 49: ...RESET output requires a pull up resistor that can be connected to a voltage higher than VCC The MAX803 MAX809 have an active low RESET output while the MAX810 has an active high RESET output The reset comparator is designed to ignore fast transients on VCC and the outputs are guaranteed to be in the correct logic state for VCC down to 1V Low supply current makes the MAX803 MAX809 MAX810 ideal for ...

Страница 50: ...terrestrial channels for DVB T system Receiving Channel 47 MHz 862 MHz Intermediate Frequency Digital center 36 125 MHz Input Impedance 75Ω Unbalanced IF Output Impedance 75Ω Balanced Loop through RF output Impedance 75Ω Unbalanced Band Change Over System PLL system Tuning System PLL system Pin out for the port to control the switchable saw 12 11 2 Pin Description ...

Страница 51: ...ly The following menu appears on the screen After entering the Service menu you can access its items by pressing buttons In order to enter selected menu use buttons To exit the service menu press M button Entire service menu parameters of TFT TV are listed below 13 1 ADJUST MENU SETTINGS In order to enter Adjust menu move the cursor to Adjust parameter by pressing buttons in Service Menu and press...

Страница 52: ...s with APS menu at Start up A P S On Off Enables disables Automatic Programming System Headphone On Off Enables disables the usage of the HP and HP related items in sound menu Vsr On Off Enables disables Vsr Virtual surround DBE On Off Enables disables DBE Dynamic Bass Enhancement Subwoofer On Off Enables disables Subwoofer Lineout On Off Enables disables Lineout Dolby prologic On Off Enables disa...

Страница 53: ...les NZ Standard NM On Off Enables disables NM Standard FM Prs Avl On Adjusts the FM Prescaler value when Automatic Volume Levelling is On Min Value 0000 00000 Max Value 00FF 00255 Options Equalizer BG DK I L L AUS NZ NM FM Prs Avl On 017 Off Options FM Prs Avl On Nicam Prs Avl On Scart Prs Avl On Scart Volume Avl On FM Prs Avl Off Nicam Prs Avl Off Scart Prs Avl Off Scart Volume Avl Off HOTEL VoD ...

Страница 54: ...djusts the FM Prescaler value when Automatic Volume Levelling is Off Min Value 0000 00000 Max Value 00FF 00255 Nicam Prs Avl Off Adjusts the Nicam Prescaler value when Automatic Volume Levelling is Off Min Value 0000 00000 Max Value 00FF 00255 Scart Prs Avl Off Adjusts the Scart Prescaler value when Automatic Volume Levelling is Off Min Value 0000 00000 Max Value 00FF 00255 Scart Volume Avl Off Ad...

Страница 55: ...q Adjusts the IF Frequency Min Value 0000 00000 Max Value 00FF 00255 Sound On Off Enables disables Sound Carrier On Off Enables disables sound Carrier feature RC_Options On Off Enables disables Remote control usage for Service menu AV 1 On Off Enables disables AV 1 AV 2 On Off Enables disables AV 2 S VIDEO On Off Enables disables S VIDEO AV 3 On Off Enables disables AV 3 PC On Off Enables disables...

Страница 56: ...00001 Disable 00000000 HOTEL MODE Enables disables Hotel mode Enable 00000001 Disable 00000000 X Not used LDLY Adjusts the Luna chroma DeLaY value Min Value 0000 00000 Max Value 0008 00008 AGC Adjusts the Automatic Gain Control value Min Value 0000 00000 Max Value 001F 00031 Options AV 3 PC MENU MIX HOTEL MODE X X X LDLY AGC 050 0012 00018 ...

Страница 57: ...sor to Aps Wss Test parameter by pressing buttons in Service Menu and press button The following menu appears on the screen There are 7 items in the Aps Wss Test menu Programme Search VPS Pdc Format 1 Pdc Format 2 Name Wss Aps Wss Test Programme Search VPS Pdc Format 1 Pdc Format 2 Name Wss CNN S 04 BG 463 P 08 ...

Страница 58: ...L BOARD ITU 656 8 bit Txt RGB FB MAIN L R POWER REGULATORS 2 5V 3 3V 5V 8V 12V 33V AUDIO AMPLIFIER 2x3W TUNER IF PROCESSOR VIDEO SWITCH 2 X RGB SWITCH VIDEO PROCESSOR AUDIO PROCESSOR HP PREAMPLIFIER AUDIO SWITCH MICROCONTROLLER SOFTWARE ROM EEPROM SCALER IC OSD IC 2M X 32 SDRAM TRIPLE ADC or DVI RECEIVER IC LVDS TRANSMITTER IC Selected video ...

Страница 59: ...UT_V C Y CVBS PIP_CVBS_EXT MAIN TUNER CVBS_IF CVBS TDA 9886 IF VPC 3230D Video pro PI5V330 RGB SWITCH SC2_RGB FB RGB_SW SC_RGB TEA 5114 RGB SWITCH TEXT_FB RGB FB TEXT RGB MSP 3410G Audio Pro QSS SC1_L R SC2_L R FAV_L R PC_L R MONO_MAIN 4053 AUDIO SWITCH MONO_PIP AM_MONO 1308T HP IC MAIN L R OPTIONAL MONO_MAIN PING_L R OPTIONAL PING I2S I2C 3 3V 5V 8V 12V 33V RGB_SW RESET YUVIN SC_FB1 AGC HS VS SC_...

Страница 60: ...2Mx32 SDRAM ADC AD9883 YUV 4 2 2 8 bit YUV 4 2 2 8 bit HS VS SDA5550 MCU 4 4 4RGB 24 bit 3x8 bit RGB TF T LC D PA NE L Selected Video Txt RGB FB I2C 256K 512K ROM Address Data Bus 8K 16K EEPROM Control Signals Analog PC input RGB 3 X 1 bit OSD IC MC141585 OPTIONAL HS VS LVDS ...

Страница 61: ...57 22 TFT TV Service Manual 13 10 2004 POWER AUDIO AMP BOARD AN7522N AUDIO AMPL MAIN L R MUTE ST BY SPEAKER L SPEAKER R REGULATORS ST BY 14V 5V 3 3V 2 5V 8V 33V 12V 14V ...

Страница 62: ...58 22 TFT TV Service Manual 13 10 2004 14 2 DIGITAL ...

Страница 63: ...59 22 TFT TV Service Manual 13 10 2004 15 CIRCUIT DIAGRAMS 15 1 ANALOG 17AMP08 001 ...

Страница 64: ...60 22 TFT TV Service Manual 13 10 2004 17AMP08 002 ...

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Страница 72: ...68 22 TFT TV Service Manual 13 10 2004 15 2 DIGITAL ...

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