TCL L42HDM61, Руководство по обслуживанию, Страница: 19 / 90

5.2 U4/U5
The Hynix HY5DU281622ET air a 134,217,728-bit CMOS Double Data Rate(DDR)
Synchronous DRAM,ideally suited for the main memory applications which requires large
memory density and high bandwidth.
The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both
rising and falling edges of the clock.While all addresses and control inputs are latched on the
rising edges of the CK(falling edges of the /CK),Data,Data strobes and Write date masks inputs
are sampled on both rising and falling edges of it.The data paths are intermally pipelined and 2-bit
prefetched to achieve very high bandwidth.All input and output voltage levels are compatible with
SSTL_2.
Block Diagram 8M*16
19