Takenaka System FS2300DV, Инструкция по эксплуатации, Страница: 29 / 37

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8. Timing Chart
●
Pixel clock timing (common in various operation modes)
[Phase relationship between clock output and data]
(Note) The above timing represents the signal timing before being encoded to serial data by the channel link device on the
side of the sending end (the part circled in the above right figure). If signal conversion from serial to parallel is made by
a channel link device in accordance with the Camera Link standard on the side of the receiving end, the phase
relationship between the clock and the data after decoding will be different from that of the above timing due to the
structural nature of a channel link device. (In the case of the output from a channel link device, the data are aligned
with the trailing edge of the clock signal.) As a general rule, this variation in timing is correctly adjusted at the capture
timing of a capture board, the equal definition file to that of the conventional parallel output type can be used for
capturing.
(Note) When a channel link device is mounted directly to the capture interface on the user side, instead of using a
commercially available capture board that supports Camera Link, it is necessary to pay close attention to the
descriptions of the data sheet of the channel link device including the phase relationship between data and clock prior to
the use.
●
Horizontal timing
ＨＤ
ＣＣＤ output signal
ＯＢ
５
Ho rizontal transfer
su spension time Dummy
bit
ＯＢ
４８ ２ ０４
２８
１ ２
１
１ ９ ３
Effective pixels
２ ９ ２
１ H or i zo nt a l p er io d （ １ Ｈ ）
２ ４
３
５
１
６
２
８
（I nt er nal h or iz ont al
s yn c sig na l ）
１ ９ ２ ０
１
６
２
８
※Unless oth erwise specified, the time unit of the numerical values
in the ho rizontal timing chart is PCLK(*).
Ｂａｙｅｒ
Effective image duration(１６２８）
１ ２ ４
３
５
４ ３
１ ６ ２ ８
１
６
２
８
２ ７ ３
Camera Link
ＬＶＡＬ
Digital output
２ ９ ２
Effective image duration（１６２８）
1/48.1MHz = 20.8nS
１６２８
１
２
１
３
１ ２ ４
３
５
１ ６ ２ １
ＲＧＢ
Effective image duration(１６２１）
２ ８ ６
１
６
２
１
Ｇ
Ｂ
Ｒ
* The numbers shown here are design values, and the actual equipment should be checked for the details.
(Note) Excluding the case that the trigger signal (Vint) is input permitting H-reset in the asynchronous shutter mode.
1 PCLK＝20.8ns
10 ns (max)
Cl o ck ou tp u t
Di g it a l da t a
１ ２ ｂ ｉ ｔ ／
１ ０ ｂ ｉ ｔ ／
８ ｂ ｉ ｔ
PCLK
Ca mera Lin k
Co nnector
C
h
an
n
el
L
in
k
(LDV,FDV)
C
a
m
e
ra
L
in
k
B
a
s
e
C
o
n
fi
g
r
at
io
n
DEMULTIPLEX.
12/10/8bit
PCLK
1／2
CLK
Ａ／Ｄ
10bit