7. Appendix B. SDK Memory Map
Table 2. SCR1 SDK Memory Map
Base
Address
Length
Name
Description
0x00000000 256 MB
Reserved
Reserved for onboard DDR3L SDRAM.
0xF0000000 64 kB
TCM
SCR1 Tightly-Coupled Memory (refer to SCR1 EAS for
details).
0xF0040000 32 B
Timer
SCR1 Timer registers (refer to SCR1 EAS for details).
0xFF000000
MMIO BASE Base address for Memory-Mapped Peripheral IO
resources, resided externally to SCR1 core.
0xFF000000 4 kB
SYS_ID
32-bit System ID register.
0xFF001000 4 kB
BLD_ID
32-bit Build ID register.
0xFF010000 4 kB
UART
16550 UART registers (refer to Xilinx IP description for
details). Interrupt line is assigned to IRQ[0].
0xFF020000 4 kB
LED
LED PIO registers: PIO_LED_RGB and PIO_LED (offsets
0x0, 0x8).
0xFF021000 4 kB
BTN
Push Button PIO register: PIO_PBUTTON. Has
associated interrupt line assigned to IRQ[1].
0xFFFF0000 64 kB
SRAM
Onchip SRAM containing pre-programmed SCR Loader
firmware. SCR1_RST_VECTOR and
SCR1_CSR_MTVEC_BASE are both mapped here:
• SCR1_RST_VECTOR = 0xFFFFFF00
• SCR1_CSR_MTVEC_BASE = 0xFFFFFF80
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