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Shanghai SVA NEC
Liquid Crystal Display Co., Ltd.
Pa
Pb
Sa
Sb
|Pa - Pb| / Pb × 100
İ
5%
|Sa - Sb| / Sb × 100
İ
5%
Pa: Supply voltage/current peak for positive, Pb: Supply voltage/current peak for negative
Sa: Waveform space for positive part, Sb: Waveform space for negative part
Note4: In case “FO” is not the recommended value, beat noise may display on the screen, because of interference
between “FO” and “1/th”. Recommended value of “FO” is as following.
FO = 1/4 × 1/th × (2n-1)
Th: Horizontal signal period(See
“4.
˔
.1 Timing characteristics”.)
n: Natural number (1, 2, 3 ……)
4.4 POWER SUPPLY VOLTAGE SEQUENCE AND RIPPLE
4.4.1 Power supply voltage sequence
*1. When VDD is on, but the value is lower than 4.5V, a protection circuit may work, then the module may
not display.
*2 The signal line is not connected with the module, at the end of cable the terminal resistor of 100 should
be added.
Note1: Display signals (D0+/-, D1+/-, D2+/-, D3+/- and CK+/-) must be “0” voltage, exclude the VALID
period (See above sequence diagram). If these signals are higher than 0.3 V, the internal circuit is
damaged.
If some of display signals of this product are cut while this product is working, even if the signal input
to it once again, it might not work normally. If customer stops the display signals, they should cut
90%
10%
90%
4.5V
0V
20
˘
t
˘
50ms
0
˘
t
˘
50ms
90%
10%
t
˘
10ms
*
1
VDD
OFF
Toff
˚
1000ms
10%
VALID
0.47ms
˘
Tr
˘
10ms
ON
0V
4.0V
90%
90%
90%
t
˚
200ms
t
˚
200ms
0.01<Tf
˘
10ms
Display Signals *2
Backlight signal