Supero SUPER S2QE6, Руководство пользователя

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S
UPER S2QR6/S2QE6 Manual
4-10
BIOS
Write Combining for P6-to-PCI:
The settings for this option are
Enabled
or
disabled.
This bit enables or
disables the combining (bursting) of accesses within the PCI memory
regions. The BWCR register provides the write combining enable/disable
bit for each region. This bit acts as a master bit to enable the write
combining for all the regions.
The main memory system of the CNB30 supports various clock speeds
and memory speeds. The MTCR (Memory Timing Control Register)
dictates the memory controller to generate the DRAM timing accordingly.
Act to Deact
The settings for this option are 6CLKS or 5CLKS .
Act to Read/Write
The settings for this option are
3CLKS
or
2CLKS
.
RAS Precharge Time
This option defines the RAS Precharge Time. The settings are
3 CLKS
,
and 2 CLKS.
RAS Cycle Time
This option defines the RA Cycle Time. The settings are
10CLKS, 9CLKS,
8CLKS, 7CLKS.
Write to DeAct
The settings for this option are 3CLKS and 2CLKS .
SDRAM CAS Latency
The settings for this option are CAS Latency3 and CAS Latency2 .
Memory Auto Precharge
The settings for this option are Enabled and Disabled .
SDRAM Fast Timing
The settings for this option are 10-1-1-1 and 11-1-1-1 . When the value
set to 10-1-1-1, the CNB30 drives the CAS# signal one clock earlier and
reduces the lead time of a page hit read by one clock.
Memory Write Posting
The settings for this option are
Enabled
and
disabled
.
ISA IO Cycle Delay
Settings include Full Delay , 1.5 BCLK, 2.5 BCLK and 3.5 BCLK.