Supero SUPER P4DPL-8GM, Руководство пользователя

Страница: 19 / 86

Chapter 1: Introduction
1-13
Introduction
1-2 Chipset Overview
The Intel E7500 (Plumas) chipset is a high-performance chipset with a per-
formance and feature-set designed for mid-range, dual processor servers.
The E7500 chipset consists of four major components: the Memory Control-
ler Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0
(P64H2) and the 82808AA Host Channel Adapter (VxB).
The MCH has four hub interfaces, one to communicate with the ICH3 and
three for high-speed I/O communications. The MCH employs a 144-bit wide
memory bus for a DDR-200 memory interface, which provides a total band-
width of 3.2 GB/s. The ICH3 interface is a 266 MB/sec point-to-point con-
nection using an 8-bit wide, 66 MHz base clock at a 4x data transfer rate.
The P64H2 interface is a 1 GB/s point-to-point connection using a 16-bit
wide, 66 MHz base clock at a 8x data transfer rate.
The ICH3 I/O Controller Hub provides various integrated functions, including
a two-channel UDMA100 bus master IDE controller, USB host controllers, an
integrated LAN controller, a System Management Bus controller and an
AC'97 compliant interface.
The P64H2 PCI-X Hub provides a 16-bit connection to the MCH for high-
performance I/O capability and two 64-bit PCI-X interfaces.
1-3 Special Features
ATI Graphics Controller
The P4DPL-8GM/P4DPL-iGM/P4DPL-M has an integrated ATI video controller
based on the Rage XL graphics chip. The Rage XL fully supports sideband
addressing and AGP texturing. This onboard graphics package can provide
a bandwidth of up to 512 MB/sec over a 32-bit graphics memory bus.
BIOS Recovery
The BIOS Recovery function allows you to recover your BIOS image file if
the BIOS flashing procedure fails (see Section 3-3).