Supermicro X7DWT, Руководство пользователя

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Chapter 1: Introduction
1-9
1-2 Chipset Overview
Built upon the functionality and the capability of the 5400 chipset, the X7DWT/
X7DWT-INF motherboard provides the performance and feature set required
for dual processor-based servers with configuration options optimized for
communications, presentation, storage, computation or database applications.
The 5400 chipset supports single or dual Xeon 64-bit Quad-Core/Dual-Core
processor(s) with a front side bus speeds of up to 1.600 GHz. The chipset consists
of the 5400 Memory Controller Hub (MCH) and the Enterprise South Bridge 2
(ESB2).
The 5400 MCH chipset is designed for symmetric multiprocessing across two
independent front side bus interfaces. Each front side bus uses a 64-bit wide,
1600 MHz data bus to transfer data. The MCH chipset connects up to eight Fully
Buffered DIMM modules, providing a total memory of up to 64 GB for DDR2 FBD
800/667/533 MHz. The MCH chipset also provides one x8 PCI-Express and one
x4 ESI interfaces to the ESB2. In addition, the 5400 chipset offers a wide range of
RAS features, including memory interface ECC, x4/x8 Single Device Data Correc-
tion, CRC, parity protection, memory mirroring and memory sparing.
Xeon Quad-Core/Dual-Core Processor Features
Designed to be used with conjunction of the 5400 chipset, the Xeon Quad-Core/
Dual-Core Processor provides a feature set as follows:
Xeon Quad-Core/Dual-Core Processors
L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
L2 Cache Size: 4MB/2MB (per core)
Data Bus Transfer Rate: 8.5 GB/s
Package: FC-LGA6/FC-LGA4, 771 Lands