60
Super X11DDW-L/NT User's Manual
JBMC_DEBUG
SRW1
JM2_1
JUIDB1
JP3
FAN5
FAN6
FAN4 FAN3
FAN2 FAN1
JBT1
LE3
LE1
C
A
LEDM1
LE2
JNVI2C1
JIPMB1
JNVI2C2
JPME2
JPME1
T-SGPIO3
BT1
+
JSTBY1
JD1
1
JL1
JP2
JF1
JPWR1
JPWR2
JPI2C1
JPWR3
JTPM1
VROC (JRK1)
JSXB1_2
JAOM
JSXB1_1
JSXB1_3
BAR CODE
X11DDW-L
REV:1.02
MAC CODE
DESIGNED IN USA
BIOS LICENSE
I-SATA 4~7
I-SATA 0~3
S-SATA 0~3
P1_NVME1
P1_NVME0
P2_NVME1
P2_NVME0
CPU2_POR
T2A
CPU2_POR
T2B
CPU2_POR
T2C
CPU2_POR
T2D
CPU1_POR
T3C
CPU1_POR
T3D
CPU1_POR
T3C
CPU1_POR
T3D
CPU1_POR
T3B
CPU1_POR
T3A
CPU1_POR
T3B
CPU1_POR
T3A
SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16
CPU2_POR
T3
SXB2:CPU2 PCI-E 3.0 X16
USB4/5(3.0)
USB0/1(3.0)
USB2/3
(3.0)
S-SA
TA5
S-SA
TA4
VGA
LAN1
LAN2
X NMI
PWR
LED
NIC HDD
LED
NIC
2
1
UID
LED
PS
FAIL
PWRRST
ON
IPMI_LAN
JWD1 JBR1
C621
10G PHY
BMC
CPU1
CPU2
P2 DIMM D1
P2 DIMM E1
P2 DIMM F1
P2 DIMM C1
P2 DIMM B1
P2
DIMM A1
P1 DIMM F1 P1 DIMM E1 P1 DIMM D1
P1
DIMM A1
P1 DIMM B1
P1 DIMM C1
JPL1
1. NVMe I
2
C1 Header
2. NVMe I
2
C2 Heade
3. P1_NVME0 Slot
4. P1_NVME1 Slot
5. P2_NVME0 Slot
6. P2_NVME1 Slot
1
2
3
4
6 5
= Available on (-NT) model only.
NVMe SMBus Headers
NVMe SMBus (I
2
C) headers (JNVI
2
C1/2), used for PCI-E SMBus clock and data connections,
provide hot-plug support via a dedicated SMBus interface. This feature is only available for a
Supermicro complete system with an SMCI-proprietary NVMe add-on card and cable installed.
See the table below for pin definitions.
NVMe Connectors
Use the two NVMe connectors (P1_NVME0 and P1_NVME1) to attach high-speed PCI-E
storage devices. When installing an NVMe device on a motherboard, please be sure to
connect the first NVMe port (P1_NVME0) first for your system to work properly.
NVMe SMBus Header
Pin Definitions
Pin#
Definition
1
Data
2
Ground
3
Clock
4
VCCIO
Содержание X11DDW-L/NT
Страница 1: ...USER S MANUAL Revision 1 3b X11DDW L NT...