2-28
X10DRL-CT/-iT/-C Motherboard User’s Manual
SAN MAC
BIOS LICENSE
SAS CODE
M
AC C
ODE
IP
MI C
ODE
BAR C
ODE
UID
LEDPWR
LEDBMC
JUSBRJ45
FAN6
FAN5
FAN1
FANB
FAN2
FAN3
FAN4
FANA
JIP
MB1
JNVI2C1
JVRM2
JPT
G1
1
JPB1
3
JPF1
JPF2
JPG1
JBR1
JPME2
JI2C1
JI2C2
JPS1
JPL2
JPL1
JVRM1
JWD1
J24
1
13
12
24
1
J7
J5
JS18
JF1
JPWR2
JPWR1
1
JL1
J21
JPI2C1
24
JPS7
SP1
BT1
+
JLAN3
JUIDB1
JSD1
JS1
JSTB
Y1
I-SGPIO1
I-SGPIO2
J25
JTPM1
JVGA
JLAN1
JB
T1
I2C BUS FOR PCI-E SLOT
1-2:ENABLE
2-3:DISABLE
X10DRL-CT
DESIGNED IN USA
REV:1.00
CHASSIS INTRUSION
JL1
2-3:DISABLE
1-2:ENABLE
JI2C1/JI2C2
1-2:NORMAL
2-3:BIOS RECOVERY
JBR1
2-3:ME MANUFACTURING MODE
JPME2
1-2:NORMAL
1-2 ENABLE
JPL2 LAN
2-3 DISABLE
JPL1/
JPI2C1:PWR I2C
JPG1:VGA
JPB1:BMC
2-3 DISABLE
1-2 ENABLE
2-3 DISABLE
1-2 ENABLE
JPTG1:10Gb LAN
2-3 DISABLE
1-2 ENABLE
JPS1:SAS
L-SAS0-3
L-SAS4-7
USB8/9(3.0)
PCI-E 3.0 X8
LAN4
LAN3
LAN1
USB12/13(3.0)
I-SA
TA0
I-SA
TA1
I-SA
TA2
I-SA
TA3
USB2/3
USB4
JTPM1:TPM/PORT80
CHASSIS INTRUSION
I-SA
TA4
CMOS CLEAR
I-SA
TA5
CPU2 SL
O
T4
SPEAKER-PIN 4-7
JD1:
PWR LED-PIN 1-3
2-3:NMI
JWD1:WATCH DOG
1-2:RST
CPU1 SL
O
T5 PCI-E 3.0 X16
CPU1 SL
O
T6 PCI-E 3.0 X8
RST
PWR
ON
JF1
P1-DIMMD1
P1-DIMMC1
X
NIC
OH/
2
FF
HDD
NIC
LED
1
PWR
LED
NMI
X
P2-DIMMF1
P2-DIMME1
CPU2
VGA
CPU1
P1-DIMMB1
P1-DIMM
A1
P2-DIMMH1
P2-DIMMG1
COM1
IPMI_LAN
LAN2
JD1
A
A. TPM/Port 80 Header
B. TFM Connector
TPM/Port 80 Header
A Trusted Platform Module/Port 80
header is located at JTPM1 to provide
TPM support and Port 80 connection.
Use this header to enhance system
performance and data security. See
the table on the right for pin defini
-
tions.
TPM/Port 80 Header
Pin Definitions
Pin # Definition
Pin # Definition
1
LCLK
2
GND
3
LFRAME#
4
<(KEY)>
5
LRESET#
6
+5V (X)
7
LAD 3
8
LAD 2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SMB_CLK4
14
SMB_DAT4
15
+3.3V_STBY
16
SERIRQ
17
GND
18
CLKRUN# (X)
19
LPCPD#
20
LDRQ# (X)
B
LSI SAS 3108 TFM Connector
The TFM connector is used to attach
a TFM module and SuperCap to the
motherboard for LSI CacheVault tech
-
nology support.