1-14
X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual
1-2 Processor and Chipset Overview
Built upon the functionality and capability of the Intel® E5-2600v3/v4 Series
processors (Socket R3) and the Intel® PCH C612, the X10DRG-O(T)+-CPU/
X10DRG-O-PCIE platform provides the best balanced solution of performance,
power ef
fi
ciency, and features to address the diverse needs of next-generation
computer users.
With support of new Intel® Microarchitecture 22nm (E5-2600v3)/14nm (E5-
2600v4) Processing Technology, the X10DRG-O(T)+-CPU/X10DRG-O-PCIE dra-
matically increases performance for a multitude of server applications.
The PCH C612 chip provides Enterprise SMbus and MCTP support with the fol-
lowing features included:
•
DDR4 288-pin memory support
•
Support for MCTP protocol and ME
•
GSX capable of GPIO expansion
•
Improved I/O capabilities to high-storage-capacity con
fi
gurations
•
SPI enhancements
•
Intel® Node Manager 3.0
•
BMC supports remote management, virtualization, and the security package
for enterprise platforms
Notes
:
1. E5-2600v4 requires Revision 2.0 BIOS (or higher).
2. Intel® Node Manager 3.0 support depends on the power supply used
in the system.
