Supermicro SUPERSERVER 6022P-6, Руководство пользователя

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S
UPER
S
ERVER 6022P-6 Manual
1-4
1-3 Mainboard Features
At the heart of the SuperServer 6022P-6 lies the P4DP6, a dual Xeon pro-
cessor motherboard designed to provide maximum performance. Below are
the main features of the P4DP6.
Chipset
The P4DP6 is based on Intel's E7500 ("Plumas") chipset, which is a high-
performance core logic chipset designed for dual-processor servers.
The E7500 chipset consists of four major components: the Memory Control-
ler Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0
(P64H2) and the 82808AA Host Channel Adapter (VxB).
The MCH has four hub interfaces, one to communicate with the ICH3 and
three for high-speed I/O communications. The MCH employs a 144-bit wide
memory bus for a DDR-200 memory interface, which provides a total band-
width of 3.2 GB/s. The ICH3 interface is a 266 MB/sec point-to-point con-
nection using an 8-bit wide, 66 MHz base clock at a 4x data transfer rate.
The P64H2 interface is a 1 GB/s point-to-point connection using a 16-bit
wide, 66 MHz base clock at a 8x data transfer rate.
The ICH3 I/O Controller Hub provides various integrated functions, including
a two-channel UDMA100 bus master IDE controller, USB host controllers, an
integrated LAN controller, a System Management Bus controller and an
AC'97 compliant interface.
Each of the three P64H2 PCI-X Hubs provides a 16-bit connection to the
MCH for high-performance IO capability and two 64-bit PCI-X interfaces.
Processors
The P4DP6 supports single or dual Xeon 512k L2 cache processors of up to
2.20 GHz+ with a 400 MHz FSB. Please refer to the support section of our
w e b s i t e f o r a c o m p l e t e l i s t i n g o f s u p p o r t e d p r o c e s s o r s ( h t t p : / /
www.supermicro.com/TechSupport.htm).