Supermicro SUPERSERVER 6013P-i, Руководство пользователя

Страница: 12 / 102

S
UPER
S
ERVER 6013P-i Manual
1-2
1-2 Serverboard Features
At the heart of the SuperServer 6013P-i lies the X5DPR-iG2, a dual Intel
Xeon processor serverboard designed to provide maximum performance.
Below are the main features of the X5DPR-iG2.
Chipset
The X5DPR-iG2 is based on Intel's E7501 chipset, which is a high-perfor-
mance core logic chipset designed for dual-processor servers. See Figure
1-1 for a block diagram of the E7501 chipset.
The E7501 chipset consists of four major components: the Memory Control-
ler Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0
(P64H2) and the 82808AA Host Channel Adapter (VxB).
The MCH has four hub interfaces, one to communicate with the ICH3 and
three for high-speed I/O communications. The MCH employs a 144-bit wide
memory bus for a DDR-266 (PC2100) memory interface, which provides a
total bandwidth of up to 4.2 GB/s. The ICH3 interface is a 266 MB/sec
point-to-point connection using an 8-bit wide, 66 MHz base clock at a 4x
data transfer rate. The P64H2 interface is a 1 GB/s point-to-point connec-
tion using a 16-bit wide, 66 MHz base clock at a 8x data transfer rate.
The ICH3 I/O Controller Hub provides various integrated functions, including
a two-channel UDMA100 bus master IDE controller, USB host controllers, an
integrated LAN controller, a System Management Bus controller and an
AC'97 compliant interface.
The P64H2 PCI-X Hub provides a 16-bit connection to the MCH for high-
performance IO capability and the 64-bit PCI-X interface.
Processors
The X5DPR-iG2 supports single or dual Intel 604 and 603-pin Xeon proces-
sors of up to 3.06 GHz at a 533/400 MHz FSB. Please refer to the support
section of our web site for a complete listing of supported processors
(http://www.supermicro.com/TechSupport.htm).