Supermicro Supero X7DVL-E, Руководство пользователя

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Chapter 1: Introduction
1-9
1-2 Chipset Overview
Built upon the functionality and the capability of the 5000V (Blackford-VS) chipset,
the X7DVL-E motherboard provides the performance and feature set required for
dual processor-based servers with confi guration options optimized for communica-
tions, presentation, storage, computation or database applications. The 5000V
(Blackford-VS) chipset supports a single or dual Dempsey/Woodcrest 64-bit dual
core processor(s) with front side bus speeds of up to 1.333 GHz. The chipset con-
sists of the 5000V (Blackford-VS) Memory Controller Hub (MCH), and the Enterprise
South Bridge 2 (ESB2).
The 5000V (Blackford-VS) MCH chipset is designed for symmetric multiprocessing
across two independent front side bus interfaces. Each front side bus uses a 64-bit
wide, 1333 MHz data bus that transfers data at 10.7 GB/sec. The MCH chipset con-
nects up to six Fully Buffered DIMM modules, providing a total memory bandwidth of
up to 17.0 GB/s. The MCH chipset also provides one x8 PCI-Express and one x4
ESI interfaces to the ESB2. In addition, the 5000V (Blackford-VS) chipset offers a
wide range of RAS features, including memory interface ECC, x4/x8 Single Device
Data Correction, CRC, parity protection, memory mirroring and memory sparing.
The Xeon Dual Core Processor Features
Designed to be used with conjunction of the 5000V chipset, the Xeon dual core
Processor provides a feature set as follows:
The Xeon Dual Core Processors
*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
*L2 Cache Size: 4MB/2MB (per core)
*Data Bus Transfer Rate: 8.5 GB/s
*Package: FC-LGA6/FC-LGA4, 771 Lands