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Chapter 2: Installation
TPM/Port 80 Header
A Trusted Platform Module (TPM)/Port 80 header is located at JTPM1 to provide TPM support
and a Port 80 connection. Use this header to enhance system performance and data security.
Refer to the table below for pin definitions.
BAR CODE
MADE IN USA
X11SDV-8C-TP8F
REV:1.02
2
1
JSIM1
G2
G3
G4
G1
S3
S5
S6
S1
S2
S4
S-SA
TA0
S-SA
TA1
S-SA
TA3
S-SA
TA2
LEDT1
C
A
LEDT3
A
C
LED3
A
C
LED1
A
C
LED2
A
C
JMD1_SR
W1
JMD2_SRW1
PRESS FIT
PRESS FIT
JPH1
JMD2
2
JPV1
BT1
SFP1
PRESS FIT
JSMB1
1
JI2C1
JPL1
JI2C2
JPME2
1
JWD1
JPUSB1
LEDM1
LEDT4
A
C
LEDT2
A
C
JMP1
JLANLED1
CPU SLOT6 PCI-E 3.0 X16
JL1
JPW1
JPI2C1
JTPM1
JBT1
JPG1
JNS1
JTGLED2
JTGLED1
JIPMB1
COM1
JSD1
JF1
16
JD1
FANB
FANA
FAN4
FAN3
FAN1
FAN2
JMP1_SR
W1
JMP1_SR
W2
:LEDPWR
I-SATA4-7
I-SATA0-3
M.2-H
PCI-E 3.0 X2/S-SATA4
CPU
UID
VGA
DIMMB1
DIMME1
USB 0/1
USB 2/3
DIMMD1
DIMMA1
PCI-E 3.0 X1
CPU SLOT6 PCI-E 3.0 X16
CPU SLOT7 PCI-E 3.0 X8
2-3:DISABLE
1-2:ENABLE
JPB1:(debug only)
PCI-E 3.0 X4 / S-SA
TA5
JMD1:M.2-HC
1-3:PWR LED
4-7:SPEAKER
:SUPER DOM
PWR
ON
OH
FF
X
RST
NIC1
NIC2
JF1:
PWR
LED
LED
HDD
2-3:DISABLE 1-2:ENABLE
JPL1: LAN1/2/3/4
LAN 1/2
LAN 7/8
LAN 5/6
LAN 3/4
IPMI_LAN
USB 4/5 (3.0)
S-SGPIO1
JGP1
JSTBY1
JNVI2C1
1
1. TPM Header
2. Power SMB Header
Trusted Platform Module Header
Pin Definitions
Pin#
Definition
Pin#
Definition
1
+3.3V
2
SPI_CS#
3
RESET#
4
SPI_MISO
5
SPI_CLK
6
GND
7
SPI_MOSI
8
9
+3.3V Stby
10
SPI_IRQ#
2
System Management Bus Header
A System Management Bus header for additional slave devices or sensors is located at
JSMB1. See the table below for pin definitions.
External I
2
C Header
Pin Definitions
Pin#
Definition
1
Data
2
Ground
3
Clock
4
NC
