41
Chapter 2: Installation
Power SMB (I
2
C) Header
Power System Management Bus (I
2
C) header at JPI
2
C1 monitors the power supply, fan and
system temperatures. Refer to the table below for pin definitions.
Power SMB Header
Pin Definitions
Pin#
Definition
1
Clock
2
Data
3
Power Fail
4
Ground
5
No Connection
BIOS LICENSE
JTGLED1
JPW1
A2SDi-H-TF
REV
:1.02
DESIGNED IN USA
BAR CODE
COM1
JPI2C1
JSD1
BT1
SRW1
SRW2
PRESS FIT
JPTG1
JWD1
JPG1
JBR1
JPME2
JI2C1
JI2C2
PRESS FIT
JSAS1
PRESS FIT
JSAS2
JMD1
1
LEDT1
C
A
LEDT3
C
A
LEDT2
C
A
LEDT4
C
A
LED1
A
JD1
JSMB1
JGP1
JBT1
JPH1
JPV1
FANA
FAN3
FAN1
FAN2
JF1
JTPM1
JL1
JRT4
JRT3
I-SATA2
I-SATA1
I-SATA3
I-SATA0
UIDLED1
C
A
LEDM1
8-11
4-7
I-SATA
I-SATA
IPMI LAN
DIMMA1
DIMMA2
DIMMB2
DIMMB1
Intel SoC
FCBGA1310
AL
W
AYS POPULA
TE DIMMx1 FIRST
CPU SLOT7 PCI-E 3.0 X4
M.2:PCI-E 3.0 X2 / I-SATA
LAN4
10Gb LAN
JPTG1:
2-3:DISABLE 1-2:ENABLE
1-2:ENABLE
JI2C1:
2-3:DISABLE
JI2C2:
1-2:ENABLE
2-3:DISABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURING MODE
RST
ON
PWR
2
NIC
OH/FF
X
2-3:NMI 1-2:RST JWD1:W
ATCH DOG
PWR
1 LED
HDD
NIC
LED
JPI2C1: PWR I2C
LAN2
USB0/1
USB2/3
USB4(3.0)
UID
VGA
LAN1
LAN3
BMC
AST2400
Intel
X557-AT2
1
1. Power SMB Header
2. SMBus Header
2
System Management Bus Header
A System Management Bus header for additional slave devices or sensors is located at
JSMB1. Refer to the table below for pin definitions.
SMBus Header
Pin Definitions
Pin#
Definition
1
Data
2
Ground
3
Clock
4
No Connection
