Sundance Spas SMT398, Руководство пользователя

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Version 1.1.1 Page 21 of 38 SMT398 User Manual
CLKZBT_FB
CLKZBT
ZxDATA[15:0]
ZxADDR[20:0]
ZxWEN
ZxCE
ZxOE
ZxCS2/CS2n
ZxADV
ZxLBOn
LBOn
ADV
CS
2/C
S
2
n
OE CE
WEN
ADDR
DA
TA
ZBT1
FPGA
Clk Feedback
CLK
16
1
1
21
1
2
1
1
ZBT3 ZBT4
ZBT2
4 independent Memory
banks with their own
address, data and control
signals.
Connections for 1
memory bank only are
shown here.
Figure 6:SMT398 ZBT Memory Banks arrangement
QDR (Quad Data Rate)
Up to 8 Mbytes of
QDR (Quad Data Rate) Synchronous Pipelined Burst SRAMs
memory is provided with direct access to the FPGA. (Provision has been made to
accommodate up to 64 Mbytes of QDR when the memory chips will be available)
The QDR operation is possible by supporting DDR (Double Data Rate) read and
writes operations through separate data output and input ports with the same cycle.
Memory bandwidth is maximized as data can be transferred into SRAM on every
rising edge of the write clock, and transferred out of SRAM on every rising edge of
the read clock. (Read clock is write clock shifted of 90 degrees)