Sundance Spas SMT351 Скачать руководство пользователя страница 5 | Manualshive

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SMT351 User Manual

Table of Figures

Figure 1: SMT351 board block diagram ..................................................................... 8

Figure 2: SMT351 FPGA data flow........................................................................... 14

Figure 3: DDR SDRAM components bank organization. .......................................... 15

Figure 4: FPGA’s clock domains .............................................................................. 16

Figure 5: SMT351 connector locations ..................................................................... 20

Figure 6: TTL I/Os (JP2) pinout ................................................................................ 22

Figure 7: JTAG header (JP1) pinout......................................................................... 23

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Содержание SMT351

Страница 1: ...SMT351 User Manual...

Страница 2: ...Version 1 1 Page 2 of 24 SMT351 User Manual Revision History Date Comments Engineer Version 28 07 04 First revision JPA 1 1...

Страница 3: ...diagram 8 Block description 9 FPGA 9 Memory 9 CPLD 9 Sundance High Speed Bus 9 Comports 9 TTL I Os 9 LEDs 10 JTAG 10 Switch 10 Using the SMT351 11 FPGA Configuration 12 Reset 13 Functional descriptio...

Страница 4: ...er 0x00 18 Control register 0x02 18 Software 19 SMT351_Config 19 Definition 19 Prototype 19 Parameters 19 SMT351_Capture 19 Definition 19 Prototype 19 Parameters 19 SMT351_PlayBack 19 Definition 19 Pr...

Страница 5: ...Figure 1 SMT351 board block diagram 8 Figure 2 SMT351 FPGA data flow 14 Figure 3 DDR SDRAM components bank organization 15 Figure 4 FPGA s clock domains 16 Figure 5 SMT351 connector locations 20 Figur...

Страница 6: ...Tables of Tables Table 1 LED description 10 Table 2 configuration comport selection 12 Table 3 TIM CONFIG feature SW1 settings 13 Table 4 FPGA s clock domains description 16...

Страница 7: ...on just the rising edge potentially doubling the output A Xilinx Virtex II Pro FPGA or XC2VP20 or XC2VP30 controls input and output data flows on two Sundance High speed Bus SHB connectors This bus i...

Страница 8: ...rts SDLs J1 Top Primary TIM Connector 2x ComPorts SDLs FPGA configuration via one of six comports 40 I O pins D Clock Feedback 2 x Sundance High speed Bus Connectors 40 I O pins D Clock Feedback 128 2...

Страница 9: ...ctional 32 bit SHB interfaces are implemented on SHB connectors They run at 100 MHz giving a 400MB s data rate thru the SMT351 SHB A implements a receiver only interface while SHB B implements a trans...

Страница 10: ...tten D4 On when Control Register bit 15 is high D5 On when memory is being read back JTAG The SMT351 includes a 6 pin JTAG header 2mm DIL header which allows re programming the FPGA using a cable such...

Страница 11: ...owing are described the main features that user should keep in mind when using SMT351 SMT351 will start outputting data after half of the total amount of data to store will have been provided to it SM...

Страница 12: ...n to configure the FPGA in this way The table below gives the possible settings for SW1 Table 2 configuration comport selection Comport number Switch number 1 Switch number 2 Switch number 3 Switch nu...

Страница 13: ...fected by CONFIG CONFIG is driven from another TIM site on the carrier board for instance from a DSP module running an application See General Firmware Description for information on the DSP TIM CONFI...

Страница 14: ...flow Data input on SHB A are stored into memory and then sent to SHB B Memory is organised in two independent banks bank 0 and bank 1 Both banks are accessed at the same time so that data can be stor...

Страница 15: ...it data bus Memory components are accessed in pairs Sundance High Speed Bus SHB Data are input and output from SMT351 using the SHB protocol See SUNDANCE SHB specification for more details The SHB int...

Страница 16: ...bank 0 Memory bank 1 Mux 400 MBytes sec 400 MBytes sec Registers Com port Control words Input buffer Output buffer Input clock domain DDR SDRAM clock domain Output clock domain Figure 4 FPGA s clock...

Страница 17: ...lation The FPGA is fully designed in VHDL Synthesis and Implementation tool The design is implemented using Xilinx ISE 6 1 SP3 and synthesized with XST FPGA resource usage Follow is the device utiliza...

Страница 18: ...4 3 2 1 0 LED START ACQ RDBK EN CLR SHB R W 0 R W 0 W 1 R W 0 Field Description flags are active when 1 CLR Writing 1 to this register will reset both input and output SHBs RDBKEN Read back enable Whe...

Страница 19: ...onfigure the SMT351 Bitstream pointer to the bitstream file name SMT351_Capture Definition Triggers capture of data into the SMT351 memory Prototype void SMT351_Capture int Cp int Words Parameters Cp...

Страница 20: ...Version 1 1 Page 20 of 24 SMT351 User Manual Connector Locations Figure 5 SMT351 connector locations...

Страница 21: ...Version 1 1 Page 21 of 24 SMT351 User Manual JP2 pinout The following diagram shows JP2 s pinout...

Страница 22: ...Version 1 1 Page 22 of 24 SMT351 User Manual Figure 6 TTL I Os JP2 pinout The following table shows JP2 mapping to the FPGA Signal name FPGA pin number TTL0 AC10 TTL1 AD10 TTL2 AC11 TTL3 AD11...

Страница 23: ...JP1 pinout Figure 7 JTAG header JP1 pinout Pin number Description 1 3 3 Volts 2 TMS 3 TCK 4 TDI 5 TDO 6 Ground...

Страница 24: ...Version 1 1 Page 24 of 24 SMT351 User Manual Physical Properties Dimensions Weight Supply Voltages Supply Current 12V 5V 3 3V 5V 12V MTBF...

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