Sun Microsystems Netra T4 AC100, Руководство по обслуживанию и системе

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Chapter 10 Functional Description 10-11
Memory Timing Values
The timing values for a given configuration depend on the following factors:
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Speed of the SDRAM
The frequency of the SDRAM chip is indicated in the serial ID EEPROM on each
DIMM. When two groups of four DIMMs are present, the SDRAM speed is
considered the speed of the slowest SDRAM chip in the group.
■
DIMM implementation
The implementation of the DIMM influences the timing parameters, in the same
way that the traces on the DIMM board define the memory bus topology. The
DIMM also supports a buffer for the address and control signals. The serial ID
PROM identifies the DIMM and by default defines a given implementation.
■
System clock frequency (Sun CrossBar Interconnect frequency)
The memory bus clock generated by the CPU module is half the system clock
frequency. The timing parameters are relative to this clock.
■
System implementation
The memory subsystem implementation also defines the timing parameters. The
term “implementation” refers to the motherboard and all the chips that are part of
the memory bus. A given implementation of a Netra T4 system defines a set of
timing parameters.
■
Processor clock ratio
The UltraSPARC III module clock speed is a multiple x4, x5, or x6 of the system
clock. Timing parameters are defined in terms of processor clocks, which means
that the processor frequency must be adjusted before programming the memory
timing control registers.
10.2.3 I/O Subsystem
The I/O subsystem is designed around two bridge ASICs—system bus controller
(SBC) and PCIO-2. SBC is the bridge between the Sun CrossBar Interconnect bus and
the two PCI buses. PCIO-2 is the bridge between the 33 MHz PCI bus and USB,
10/100-Mbit Ethernet, and EBus. The graphics slot (UPA64S) is not used on the
Netra T4 system.
10.2.3.1 SBC ASIC
The SBC ASIC supports the full Sun CrossBar Interconnect protocol. The CPU
module interface to the 288-bit Sun CrossBar Interconnect data bus is through a
144-bit private data bus at 150 MHz for a maximum bandwidth of 2.4 Gbyte/sec.