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SR/AI
SR/AP
Hardware Reference
Release r09
Page 13 of 76
By holding pin B-1 (EXT-RES#)
at ≤ 0,5V for ≥ 5ms, an external reset is generated. This pin has a
fixed internal pull-up resistor (R
PU
= 30k
Ω ... 50kΩ) and a capacitor to GND (100n) which acts as
debounce filter. If EXT-RES# is not used, it may be left open.
Note:
EXT-RES# pin can also be output. Use an open drain device or push button to drive it low. EXT-
RES# must not be connected to VSUP or driven to logic high-level directly. Provide for a 1k
Ω
series resistor when driving EXT-RES# from a CMOS output.
SR
C-1,E-6,F-6
VSUP
GND
+3V3
EXT-RES#
B-1
Reset-Switch is optional
Please Note: SR has an open-drain output and approx. 40k internal pullup
1k
Reset signal is optional
Host MCU
GPIO
VDD
Figure 3: SR Example Reset
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