DocID018909 Rev 11
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RM0090
General-purpose timers (TIM9 to TIM14)
687
Note:
The states of the external I/O pins connected to the standard OCx channels depend on the
state of the OCx channel and on the GPIO registers.
19.4.8 TIM9/12
counter
(TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
19.4.9 TIM9/12
prescaler
(TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
19.4.10 TIM9/12
auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
Table 101. Output control bit for standard OCx channels
CCxE bit
OCx output state
0
Output disabled (OCx=’0’, OCx_EN=’0’)
1
OCx= Polarity, OCx_EN=’1’
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0
CNT[15:0]
: Counter value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PSC[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0
PSC[15:0]
: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded into the active prescaler register at each update event.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARR[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0
ARR[15:0]
: Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to the
Section 19.3.1: Time-base unit on page 644
for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.